Dielectric Recesses for Interconnect Breakdown Resistance
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Solution Overview
Problem
Integrated circuit (IC) interconnects face challenges with dielectric breakdown, particularly in deep-submicron process nodes, where reduced dimensions increase electric field intensity and curvature, leading to potential breakdown between adjacent interconnects, and existing solutions either reduce layout density or increase line-to-line capacitance.
Innovation Solution
Selectively etching the dielectric layer to form recesses between interconnects and depositing a high dielectric breakdown field dielectric material that conforms to the interconnect topology, encapsulating high-electric field regions to increase dielectric breakdown voltage and prevent metal diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the dielectric layer is selectively etched to form recesses and a high breakdown field dielectric material is deposited, then dielectric breakdown voltage is increased by 20-80%, but the process complexity increases due to additional etching and deposition steps
Solution Approach 1:
The patent performs preliminary etching of recesses in the dielectric layer before final dielectric deposition, preparing the structure in advance to accommodate the high breakdown field material. This preliminary action allows the subsequent deposition to conformally coat the recessed regions, ensuring enhanced breakdown protection at critical interconnect interfaces where electric field intensity is highest.
Solution Approach 2:
The patent applies different dielectric materials with different breakdown field strengths to different locations within the interconnect structure. Specifically, a high breakdown field dielectric material is deposited in the recessed regions between adjacent interconnects where electric field intensity is highest, while other regions maintain the original dielectric material, thus optimizing reliability locally without unnecessarily complicating the entire structure.
2Reliability
If spacing between interconnects is increased to reduce electric field intensity, then dielectric breakdown is reduced, but layout density decreases
Solution Approach 1:
The patent enhances dielectric breakdown resistance locally at the interfaces between adjacent interconnects by depositing high breakdown field material in recessed regions, rather than uniformly increasing spacing across the entire layout. This allows maintaining tight interconnect spacing for high layout density while providing targeted protection where electric field intensity and breakdown risk are highest.
Solution Approach 2:
The patent introduces a high breakdown field dielectric material as an intermediary layer in the recessed regions between interconnects. This intermediary material acts as an enhanced insulating barrier that prevents dielectric breakdown without requiring increased physical spacing between interconnects, thus maintaining layout density while improving reliability.
3Reliability
If a conformal dielectric layer is deposited over recesses, then dielectric breakdown performance is enhanced, but manufacturing precision requirements increase to ensure proper conformal coverage
Solution Approach 1:
The patent performs preliminary etching to create well-defined recesses with specific geometries before conformal deposition. These pre-formed recesses provide a controlled template that guides the conformal deposition process, ensuring uniform material coverage on the recessed surfaces. The preliminary structuring reduces the precision burden during deposition by providing a predetermined geometry that naturally accommodates conformal coating.
Solution Approach 2:
The patent changes the physical and chemical parameters of the dielectric material by selecting a high breakdown field material with specific deposition characteristics. This material choice enables conformal deposition with better coverage uniformity and adhesion to the recessed surfaces, reducing manufacturing precision requirements while achieving enhanced breakdown performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances dielectric breakdown performance by increasing mean and minimum breakdown voltage by 20-80% while maintaining interconnect geometry and density, improving long-term reliability and reducing capacitance.
Implementation Method 1
depositing a high dielectric breakdown field dielectric material that conforms to the interconnect topology
Implementation Method 2
depositing a high dielectric breakdown field dielectric material that conforms to the interconnect topology
Implementation Method 3
selectively etching the dielectric layer to form recesses between interconnects
Data Source
AI summary
Techniques are disclosed for enhancing the dielectric breakdown performance of integrated circuit (IC) interconnects. The disclosed techniques can be used to selectively etch the dielectric layer of an IC to form a recess, for example, between a given pair of adjacent/neighboring interconnects (e.g., metal lines). Thereafter, a layer of dielectric material of higher dielectric breakdown field (Ec) than the surrounding/underlying dielectric material (or other suitable insulator, as will be apparent in light of this disclosure) may be deposited/grown so as to substantially conform to the topology provided by the adjacent/neighboring interconnects and etched recess. In some cases, this dielectric layer may help to prevent or otherwise reduce: (1) dielectric breakdown between the adjacent/neighboring interconnects by locally increasing the dielectric breakdown voltage (VBD); and/or (2) diffusion of the interconnect fill metal into the surrounding/underlying dielectric material. In some instances, such a layer may serve as an etch stop.