Dielectric Preservation in Replacement Gate Process
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Solution Overview
Problem
In the replacement gate process for field-effect transistors, poor etch rate selectivity during reactive ion etching leads to recessing of the interlayer dielectric layer, resulting in uncontrollable gate height and topography issues, which affect transistor performance variability.
Innovation Solution
A method involving the formation of a dummy gate structure with a first and second dielectric layer, where the second dielectric layer has higher etch rate selectivity, allowing for precise control during etching processes to maintain the integrity of the sacrificial gate structures and eliminate recessing, enabling accurate gate height control and reducing topography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If reactive ion etching is used to pattern the hardmask and remove sacrificial gate structures, then the gate structure can be formed, but the interlayer dielectric layer is recessed due to poor etch rate selectivity, resulting in uncontrollable gate height and topography issues
Solution Approach 1:
A cap dielectric layer is introduced as an intermediary protective layer between the interlayer dielectric layer and the etching process. This cap layer has high etch rate selectivity, meaning it etches much slower than the interlayer dielectric, thereby protecting the underlying dielectric from recessing during the etching of sacrificial gate structures and hardmask patterning.
Solution Approach 2:
The solution changes the etch rate parameter by introducing a cap dielectric layer with significantly different etch rate characteristics compared to the interlayer dielectric layer. This parameter difference (high selectivity) allows the cap layer to protect the underlying structure during etching, thereby controlling gate height and preventing topography issues.
2Ease of operation
If chemical mechanical polishing is used to expose the sacrificial gate structure, then the gate structure can be accessed for removal, but the process introduces topography and reduces control over final gate height
Solution Approach 1:
The cap dielectric layer serves as a protective intermediary during chemical mechanical polishing. It allows the polishing process to expose the sacrificial gate structure while the cap layer itself protects the interlayer dielectric from excessive removal, thereby maintaining better control over final gate height and reducing topography.
3Ease of manufacture
If the interlayer dielectric layer is exposed to etching processes, then the sacrificial gate structures can be removed, but poor etch rate selectivity causes the dielectric to be recessed relative to the gate structures
Solution Approach 1:
The cap dielectric layer acts as a protective intermediary that allows the etching process to remove sacrificial gate structures while preventing the underlying interlayer dielectric from being recessed. The cap layer's high etch rate selectivity ensures it protects the dielectric during this removal process.
Solution Approach 2:
The cap dielectric layer is formed in advance (prior to the etching process) to protect the interlayer dielectric layer before the harmful etching action occurs. This preliminary protective action prevents the dielectric recessing issue from occurring in the first place.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures controlled gate height and reduces topography by utilizing a second dielectric layer with higher etch rate selectivity, improving the precision of gate structure formation and enhancing transistor performance consistency.
Implementation Method 1
The second dielectric layer has a higher etch rate selectivity than the first dielectric layer to the etching process
Data Source
AI summary
Structures for use in a replacement gate process involving a field-effect transistor and methods for forming such structures. A first dielectric layer is formed adjacent to a dummy gate structure, and a second dielectric layer is formed on the first dielectric layer. After the second dielectric layer is formed, a portion of the dummy gate structure is removed with an etching process to cut the dummy gate structure into disconnected segments. The second dielectric layer caps the first dielectric layer when the portion of the dummy gate structure is removed. The second dielectric layer has a higher etch rate selectivity than the first dielectric layer to the etching process.