Dielectric Segmentation for 3D Memory Plug Etching
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Solution Overview
Problem
The complexity of 3D stack memory device structures complicates manufacturing processes, making it challenging to achieve high element density and large memory capacity while maintaining cost efficiency.
Innovation Solution
A semiconductor structure is manufactured with a dielectric structure comprising distinct upper and lower dielectric portions and a dielectric layer, allowing conductive plugs to pass through and physically and electrically connect conductive structures, using a simplified etching process that reduces the number of masks and etching steps, thereby decreasing manufacturing time and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D stack memory device structures are used to increase memory capacity and element density, then memory capacity and element density are improved, but manufacturing process complexity increases
Solution Approach 1:
The dielectric structure is segmented into three distinct portions: a lower dielectric portion, a middle dielectric layer, and an upper dielectric portion. Each portion has different material composition and etching characteristics, allowing selective removal during manufacturing. This segmentation enables complex 3D stack structures to be built and modified in controlled stages, reducing overall manufacturing complexity while maintaining high element density
Solution Approach 2:
Different regions of the dielectric structure have locally optimized properties. The lower dielectric portion uses one material composition, the middle layer uses a different material with intermediate etching selectivity, and the upper portion uses yet another material. This local quality variation allows precise control over etching processes at different depths and locations, enabling complex manufacturing patterns to be executed with simpler overall processes
2Quantity of substance
If complex 3D stack structures are manufactured, then memory capacity increases, but manufacturing time and cost increase
Solution Approach 1:
The dielectric structure is pre-configured with three distinct portions having different etching selectivities before the actual plug formation process. This preliminary action allows subsequent etching and deposition steps to proceed more efficiently, as the selective removal of dielectric material can be controlled without requiring multiple separate processing cycles. The pre-established material gradient enables faster manufacturing while achieving the required 3D stack complexity for high memory capacity
Data Source
AI summary
A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a substrate, a first conductive structure, a second conductive structure, a dielectric structure, a dielectric layer, a first conductive plug, and a second conductive plug. The first conductive plug passes through only an upper dielectric portion of the dielectric structure, the dielectric layer and a lower dielectric portion of the dielectric structure to physically and electrically contact with the first conductive structure. The second conductive plug passes through the upper dielectric portion, the dielectric layer and the lower dielectric portion to physically and electrically contact with the second conductive structure.