Dielectric Slots Reduce Via Resistance in Dual Damascene Interconnects
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Solution Overview
Problem
Dual damascene vias in wide interconnect lines of integrated circuits exhibit flared profiles, leading to increased and erratic via resistance due to excess liner metal at the bottom, which is not effectively addressed by existing manufacturing processes.
Innovation Solution
Incorporating dielectric slots adjacent to dual damascene vias, laterally separated by no more than half the width of the via, to reduce flaring and thereby minimize the thickness of the dual damascene liner, thus lowering electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If dual damascene vias are formed in wide interconnect lines, then interconnect width is increased for higher current carrying capacity, but via resistance becomes higher and more erratic due to flared profiles with excess liner metal
Solution Approach 1:
The patent applies local quality by introducing dielectric slots specifically at the via locations within the wide interconnect line, rather than modifying the entire interconnect structure. This localized modification changes the etch profile only where needed, creating straighter via walls and reducing liner metal accumulation at the via bottom, thereby lowering via resistance while preserving the overall wide interconnect geometry for high current capacity
Solution Approach 2:
The dielectric slots are formed in the interconnect dielectric layer before the dual damascene via etch process. This preliminary action pre-configures the etch environment to prevent flaring during via formation, ensuring that the via walls remain straight and liner metal deposition is minimized from the outset, rather than attempting to correct the flared profile after via formation
2Ease of manufacture
If conventional dual damascene process is used without dielectric slots, then manufacturing process is simpler, but via holes exhibit flared profiles causing excess liner metal and higher via resistance
Solution Approach 1:
Rather than completely redesigning the dual damascene process, the invention introduces localized dielectric slots only at via positions within the existing process flow. This selective modification maintains the overall simplicity of the conventional dual damascene manufacturing process while precisely addressing the via profile control issue where it occurs
Solution Approach 2:
The dielectric slot acts as an intermediary structure that modifies the etch environment during via formation. By introducing this intermediate feature in the dielectric layer, the process achieves better via profile control without requiring fundamental changes to the dual damascene manufacturing sequence, maintaining ease of manufacture while improving precision
Data Source
AI summary
An integrated circuit may include dual damascene interconnects formed using a via-first dual damascene process or a trench-first dual damascene process. The via-first process may be a partial-via-first process or a full-via-first process. A trench mask for a wide interconnect line which is at least twice as wide as a dual damascene via in the wide interconnect line may have a dielectric slot adjacent to the dual damascene via. The dual damascene via is laterally separated from the dielectric slot by no more than half a width of the dual damascene via.