Dielectric Spaced Diode ESD Protection
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Solution Overview
Problem
Integrated circuits face challenges with diodes having high junction capacitance, which slows down the response to electrostatic discharge (ESD) events, leading to voltage overshoot and potential damage to sensitive device elements.
Innovation Solution
The implementation of a dielectric spacing structure between diode anode and cathode regions, using a buried layer to create a distributed parallel current path, and employing a SiBLK spacer to minimize dopant implantation and capacitance, thereby reducing junction capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If heavily doped P and N regions with large doping gradient are used in diode, then current capacity is improved, but junction capacitance increases which slows down switching speed
Solution Approach 1:
The diode structure is segmented into multiple doped regions with different doping concentrations arranged in a specific sequence (heavily doped P region, lightly doped P region, lightly doped N region, heavily doped N region). This segmentation allows the depletion region to be distributed across multiple interfaces, reducing junction capacitance while maintaining current capacity through the heavily doped contact regions.
Solution Approach 2:
Different regions of the diode are assigned different doping concentrations optimized for their specific functions: heavily doped regions for current conduction, lightly doped regions for capacitance reduction. The local doping quality varies spatially to simultaneously achieve high current capacity and low junction capacitance.
2Power
If large doping gradient is used in diode junction, then current conduction is improved, but junction capacitance increases causing voltage overshoot during ESD events
Solution Approach 1:
The doping gradient is segmented into multiple steps rather than a single large gradient. Multiple doped regions with intermediate doping concentrations are introduced to distribute the gradient, which reduces junction capacitance and minimizes voltage overshoot while still enabling effective current conduction during ESD events.
Solution Approach 2:
Lightly doped buffer regions are placed between heavily doped regions to cushion the abrupt doping gradient. These intermediate regions reduce the capacitance effect before the ESD event occurs, preventing voltage overshoot while maintaining the ability to conduct high current when needed.
3Reliability
If conventional diode structure is used for ESD protection, then circuit protection function is provided, but response time is slowed due to high junction capacitance
Solution Approach 1:
The diode is divided into multiple doped regions that create multiple depletion region interfaces. This segmentation reduces the overall junction capacitance, allowing the diode to respond faster to ESD events while maintaining its protection function. The reduced capacitance enables quicker charging and discharging during ESD strikes.
Solution Approach 2:
The doping concentration parameters are changed across different regions of the diode. By optimizing the doping concentrations and their spatial distribution, the junction capacitance is reduced, which directly improves the response time of the ESD protection circuit while maintaining adequate current handling capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a faster response to ESD events with reduced voltage overshoot and improved reliability of integrated circuits by minimizing junction capacitance and resistance, ensuring effective protection for sensitive components.
Implementation Method 1
capacitance associated with the P-N junction of the diode may be relatively large in some integrated circuits
Implementation Method 2
electrostatic discharge (ESD) protection circuitry designed to dissipate charge from an ESD strike
Data Source
AI summary
An electronic device, e.g. an integrated circuit, is formed on a P-type lightly-doped semiconductor substrate having an N-type buried layer. First and second N-wells extend from a surface of the substrate to the buried layer. A first NSD region is located within the first N-well, and a second NSD region is located within the second N-well. A PSD region extends from the substrate surface into the substrate and is located between the first and second NSD regions. A P-type lightly-doped portion of the substrate is located between the N-well and the substrate surface and between the PSD region and the first and second NSD regions.