Composite Dielectric Spacer for Low-Capacitance Contact Architecture
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Solution Overview
Problem
Miniaturized solid-state transistors face challenges with parasitic capacitance between contact via and gate metal, which increases with dimension reduction, detrimental to transistor operation.
Innovation Solution
The implementation of a composite dielectric spacer separating contact members from conductive interconnects, comprising multiple dielectric layers with varying thickness and materials, to reduce parasitic capacitance while maintaining desirable contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If transistor dimensions are reduced for miniaturization, then device size decreases and integration density increases, but parasitic capacitance between contact via and gate metal increases
Solution Approach 1:
A dielectric spacer is introduced as an intermediary element between the contact via and gate metal. This spacer physically separates the two conductive elements, reducing the parasitic capacitance formed between them while allowing the transistor dimensions to be reduced for miniaturization.
Solution Approach 2:
Instead of relying solely on horizontal separation in the plane, the solution extends the separation into the vertical dimension by adding a dielectric spacer with a specific thickness (1-5 nm). This vertical dimension approach effectively reduces capacitance without further reducing the already minimized horizontal transistor dimensions.
2Volume of moving object
If contact via dimensions are reduced to maintain miniaturization, then transistor size decreases, but contact resistance increases
Solution Approach 1:
The dielectric spacer is applied selectively only in the region where the contact via approaches the gate metal, rather than uniformly across the entire structure. This localized application reduces parasitic capacitance where needed while preserving low contact resistance at the via-semiconductor interface.
Solution Approach 2:
The dielectric spacer thickness is optimized to a specific range (1-5 nm) - thin enough to minimize capacitance reduction benefit but thick enough to provide effective separation. This partial action approach achieves the necessary capacitance reduction without excessive thickness that would compromise other device characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance by 3-6% per nanometer of the second dielectric layer, from 1 to 5 nanometers, thereby mitigating performance degradation and maintaining satisfactory contact resistance.
Implementation Method 1
capacitance between contact via and gate metal increases. Such capacitance is undesirable and detrimental to the operation of a transistor
Implementation Method 2
implementation of a composite dielectric spacer separating contact members from conductive interconnects, comprising multiple dielectric layers with varying thickness and materials
Data Source
AI summary
Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.