Dielectric-Spacer GaN FET Gates for Shorter Gate Lengths
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Solution Overview
Problem
Fabricating high-power field effect transistors (FETs) with short gate lengths using gallium nitride (GaN) on silicon carbide (SiC) substrates is challenging due to the transparency and non-uniformity of SiC substrates, and conventional anisotropic dry etch techniques can damage sensitive surfaces during material etching.
Innovation Solution
A transistor device with a multi-layer dielectric stack and dielectric spacers is fabricated, where the dielectric spacers are formed in the gate channel opening to reduce gate length and mitigate surface damage, using anisotropic dry etching with a stop etch layer protecting the substrate surface, allowing for shorter gate lengths and additional design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If conventional anisotropic dry etch techniques are used to etch material during FET fabrication, then vertical sidewalls can be formed, but ion bombardment damages sensitive surfaces of the material being etched or material beneath it
Solution Approach 1:
A protective dielectric layer is deposited over the GaN-on-SiC substrate before the anisotropic dry etching process. This preliminary protective action prevents ion bombardment damage to the substrate surface and sensitive material layers during etching, while still allowing the formation of vertical sidewalls in the dielectric stack
Solution Approach 2:
The protective dielectric layer acts as an intermediary between the ion bombardment and the sensitive GaN-on-SiC substrate. It absorbs the harmful ion bombardment while allowing the etching process to proceed vertically through the dielectric stack, thus protecting the substrate without compromising the vertical sidewall formation
2Ease of manufacture
If photolithography alone is used to fabricate FETs with short gate lengths, then the process is simpler, but it is more challenging for GaN-on-SiC substrates due to transparency and non-uniformity
Solution Approach 1:
The gate channel opening is formed through a multi-layer dielectric stack with different etch selectivities. By segmenting the dielectric structure into layers with distinct etching characteristics, the patent achieves precise gate length definition through selective etching processes, overcoming the limitations of photolithography on transparent GaN-on-SiC substrates
Solution Approach 2:
The patent utilizes etch selectivity parameters between different dielectric layers to achieve precise gate length control. By changing the etching parameters and using materials with different etch rates, the process achieves high manufacturing precision for short gate lengths that cannot be achieved with conventional photolithography alone
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach enables the achievement of shorter gate lengths and reduces surface damage during etching, improving the fabrication of power transistors and providing design flexibility by using dielectric spacers in the gate and field plate channels.
Implementation Method 1
ion bombardment typically used in such techniques can damage sensitive surfaces
Implementation Method 2
conventional anisotropic dry etch techniques allow for vertical sidewalls to be formed when etching material
Implementation Method 3
The first dielectric layer and the third dielectric layer may each have high etch selectivity with respect to the second dielectric layer
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
A transistor device includes a semiconductor substrate (110) and a gate structure (128) formed over the substrate. Forming the gate structure may include steps of forming a multi-layer dielectric stack (116, 118, 122) over the substrate, performing an anisotropic dry etch of the multi-layer dielectric stack to form a gate channel, forming a conformal dielectric layer over the substrate, performing an anisotropic dry etch of the conformal dielectric layer to form dielectric sidewalls (124) in the gate channel, etching portions of dielectric layers in a gate channel region, and forming gate metal in the gate channel region. Dielectric spacers (126) may be similarly formed in a field plate channel prior to formation of a field plate (132) of the transistor. By forming dielectric spacers in the gate channel, the length of the gate structure can be advantageously decreased.