Dielectric Spacer Gate Structure for Shorter GaN FET Fabrication
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Solution Overview
Problem
Fabricating high-power field effect transistors (FETs) with short gate lengths is challenging, especially for gallium nitride (GaN) on silicon carbide (SiC) substrates, due to transparency issues and non-uniformity of SiC substrates. Additionally, conventional anisotropic dry etch techniques can damage sensitive surfaces during material etching.
Innovation Solution
A transistor device with a multi-layer dielectric stack and dielectric spacers is fabricated. The multi-layer dielectric stack includes a first dielectric layer, a second dielectric layer, and a third dielectric layer, where the first and third dielectric layers have high etch selectivity with respect to the second dielectric layer. Dielectric spacers are formed between the gate electrode and the sidewalls of the gate channel opening, reducing the gate length and mitigating surface damage from anisotropic dry etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If conventional anisotropic dry etch techniques are used to etch material during FET fabrication, then vertical sidewalls can be formed, but ion bombardment damages sensitive surfaces of the material being etched or of material beneath
Solution Approach 1:
A multi-layer dielectric stack is introduced as an intermediary protective structure between the etch process and the sensitive substrate surface. The dielectric layers with high etch selectivity act as a buffer that absorbs ion bombardment damage while allowing the formation of vertical sidewalls in the gate channel region.
Solution Approach 2:
The multi-layer dielectric stack is formed beforehand before the anisotropic dry etch process. This preliminary protective layering ensures that when ion bombardment occurs during etching, the damage is contained within the dielectric stack rather than reaching the sensitive GaN-on-SiC substrate surface.
2Length of moving object
If photolithography alone is used for fabricating FETs with short gate lengths, then the process is simpler, but achieving short gate lengths is more challenging due to transparency of SiC substrates and lack of sufficiently uniform flatness of GaN-on-SiC substrates
Solution Approach 1:
The invention transitions from a single-layer to a multi-layer dielectric structure, adding vertical dimensionality to the fabrication process. This multi-layer stack provides additional control planes for defining gate length, enabling shorter and more precise gate lengths than achievable with conventional photolithography on single-layer substrates.
Solution Approach 2:
By introducing multiple dielectric layers with different etch selectivity parameters, the invention enables precise control of gate length through selective etching processes. The etch selectivity ratios between layers serve as controllable parameters that define the final gate dimensions, overcoming the limitations of photolithography alone.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach allows for shorter gate lengths than achievable with photolithography alone, while protecting the substrate surface from damage during etching, thereby improving the fabrication of high-power FETs.
Implementation Method 1
The first dielectric layer and the third dielectric layer may each have high etch selectivity with respect to the second dielectric layer
Data Source
AI summary
A transistor device includes a semiconductor substrate and a gate structure formed over the substrate. Forming the gate structure may include steps of forming a multi-layer dielectric stack over the substrate, performing an anisotropic dry etch of the multi-layer dielectric stack to form a gate channel, forming a conformal dielectric layer over the substrate, performing an anisotropic dry etch of the conformal dielectric layer to form dielectric sidewalls in the gate channel, etching portions of dielectric layers in a gate channel region, and forming gate metal in the gate channel region. Dielectric spacers may be similarly formed in a field plate channel prior to formation of a field plate of the transistor. By forming dielectric spacers in the gate channel, the length of the gate structure can be advantageously decreased.