Dielectric Spacer Mediator Prevents Epitaxial Extrusion in FinFET Devices

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Solution Overview

Problem

The semiconductor industry faces challenges in manufacturing low-cost, high-performance, and low-power integrated circuits due to increased complexity in the manufacturing process caused by scaling down semiconductor IC dimensions, which affects device density and reliability due to issues like epitaxial extrusion and time-dependent dielectric breakdown.

Innovation Solution

A semiconductor device structure is developed with a gate stack, spacer structure, and dielectric structure that separates ultra-low-k spacers from epitaxial structures, preventing epitaxial extrusion and enhancing device reliability through a method involving the formation of a gate stack over a fin structure, patterning spacer layers, and depositing a dielectric layer to create a recessed face, thereby preventing damage to ultra-low-k spacers and ensuring proper device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If semiconductor IC dimensions are scaled down to improve production efficiency and lower costs, then productivity increases, but manufacturing complexity increases and reliability deteriorates due to epitaxial extrusion and time-dependent dielectric breakdown

Engineering Contradiction:
Improveproduction efficiencyVSAvoiddevice reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A dielectric structure is introduced as an intermediary element positioned between the ultra-low-k spacer and the epitaxial structure. This dielectric mediator prevents direct interaction that would cause epitaxial extrusion, thereby maintaining reliability while allowing continued scaling for productivity improvement.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The device structure is segmented into distinct functional regions with the dielectric structure creating a separation between the spacer region and the epitaxial region. This segmentation isolates the ultra-low-k spacer from direct contact with the epitaxial structure, preventing harmful interactions while maintaining overall device functionality.

Inventive Principle:
Principle #1Segmentation

2Productivity

If semiconductor IC dimensions are scaled down to improve production efficiency and lower costs, then productivity increases, but manufacturing complexity increases

Engineering Contradiction:
Improveproduction efficiencyVSAvoidmanufacturing process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The manufacturing process is segmented into distinct stages with the dielectric structure formation serving as a dedicated step between spacer formation and epitaxial growth. This segmentation organizes the complex manufacturing process into manageable stages, making it easier to control and execute despite overall increased complexity from scaling.

Inventive Principle:
Principle #1Segmentation

3Quantity of substance

If ultra-low-k spacers are used in scaled-down devices, then device density is maintained, but epitaxial extrusion occurs causing reliability issues

Engineering Contradiction:
Improvedevice densityVSAvoiddevice reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The dielectric structure serves as a protective intermediary layer that physically separates the ultra-low-k spacer from the epitaxial structure. This mediation allows the ultra-low-k spacer to maintain its density-preserving function while preventing the harmful epitaxial extrusion that would compromise reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11211472B2Semiconductor device and method of forming the same
Publication Date: 2021.12.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11211472B2 patent drawing
  • US11211472B2 patent drawing
  • US11211472B2 patent drawing

AI summary

A semiconductor device includes a semiconductor substrate having a fin structure, a gate stack across the fin structure, a spacer structure on a sidewall of the gate stack, an epitaxial structure on the semiconductor substrate, and a dielectric structure in the spacer structure. The dielectric structure extends along a lower portion of the spacer structure and across the fin structure.