Dielectric Spacer Layout for Semiconductor Package Isolation

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Solution Overview

Problem

Existing semiconductor devices face challenges in achieving both increased creepage and clearance distances without enlarging the package size, which is crucial for safety and performance in polluted environments.

Innovation Solution

A semiconductor device design incorporating a dielectric spacer that is longer than the leads, positioned in cavities between leads and features like heatsinks, to enhance both creepage and clearance distances, thereby allowing for a smaller form factor and improved safety in rugged environments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a convex, balcony-like heatsink is used to move the conductive surface further away, then the clearance distance is improved, but the device complexity increases

Engineering Contradiction:
Improveclearance distanceVSAvoidheatsink structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A dielectric spacer is introduced as an intermediary component between the heatsink and the package body. This spacer physically separates the conductive heatsink surface from the leads, increasing the clearance distance without requiring complex heatsink geometries. The dielectric material provides both electrical isolation and mechanical spacing functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The safety distance enhancement is divided into two independent components: the dielectric spacer for clearance distance and surface grooves for creepage distance. This segmentation allows each feature to be optimized independently - the spacer handles the perpendicular clearance while grooves handle the surface path creepage, avoiding the need for complex integrated structures.

Inventive Principle:
Principle #1Segmentation

2Reliability

If grooves are added between leads on the package outline to increase creepage distance, then the creepage distance is improved, but the device complexity increases

Engineering Contradiction:
Improvecreepage distanceVSAvoidpackage structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The safety distance enhancement is divided into two independent components: the dielectric spacer for clearance distance and surface grooves for creepage distance. This segmentation allows each feature to be optimized independently - the spacer handles the perpendicular clearance while grooves handle the surface path creepage, avoiding the need for complex integrated structures.

Inventive Principle:
Principle #1Segmentation

3Reliability

If the package size is increased to achieve both increased creepage and clearance distances, then the safety distance is improved, but the form factor worsens

Engineering Contradiction:
Improvesafety distanceVSAvoidpackage volume
Core Design Contradiction:
ReliabilityVSVolume of moving object

Solution Approach 1:

Instead of increasing the planar footprint of the package, the solution utilizes the vertical dimension by extending the dielectric spacer perpendicular to the package body surface. This allows clearance distance to be increased in the Z-direction rather than requiring larger X-Y dimensions, thereby improving safety distance without worsening the form factor.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20260011627A1Semiconductor device with a dielectric spacer and method of manufacturing
Publication Date: 2026.01.08 INFINEON TECH AUSTRIA AG
  • US20260011627A1 patent drawing
  • US20260011627A1 patent drawing
  • US20260011627A1 patent drawing

AI summary

A semiconductor device includes a package body having a topside in a first plane and a bottom side in a second plane parallel to the first plane. At least one lead protruding out of the package body has a first portion in a plane parallel to the first plane and a second portion being bent away from the first plane towards the second plane. A cavity is positioned between the at least one lead and a feature of the semiconductor device. A removable dielectric spacer is configured to be positioned in the cavity between the at least one lead and the feature. The dielectric spacer is longer than the at least one lead.