Dielectric Inner Spacers for Nanosheet Transistor Isolation
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Solution Overview
Problem
Current semiconductor technologies face challenges in further scaling and reducing the size of field-effect transistors (FETs) beyond 7 nm, particularly in nanosheet and nanowire stacks, due to issues with parasitic epitaxy growth and uncontrolled merging of source/drain regions.
Innovation Solution
The formation of dielectric spacers around semiconductor layers in nanosheet transistors, using selective etching and conformal deposition to create continuous isolating structures that prevent parasitic source/drain epitaxial growth, ensuring electrical isolation and controlled separation of transistor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used for nanosheet transistors, then manufacturing simplicity is maintained, but parasitic epitaxy growth occurs and source/drain regions merge uncontrollably
Solution Approach 1:
Dielectric spacers are formed around semiconductor layers before source/drain region formation, preventing parasitic epitaxy growth in advance. The spacers are created through conformal deposition on sacrificial layers, establishing isolation structures before the harmful epitaxial growth can occur during subsequent processing steps.
Solution Approach 2:
Dielectric spacers act as intermediary structures between adjacent nanosheet transistor channels, physically separating source/drain regions and preventing their uncontrolled merging. These spacer structures serve as mediating elements that maintain proper spacing and electrical isolation between adjacent devices.
2Productivity
If device size is reduced for further scaling, then transistor density increases, but electrical isolation between adjacent devices becomes difficult to maintain
Solution Approach 1:
Dielectric spacers are formed by conformal deposition around semiconductor layers, creating nested structures where the spacer material surrounds the channel-forming layers. This nesting approach maximizes the use of available space while maintaining electrical isolation, enabling higher transistor density without compromising device separation.
Solution Approach 2:
The isolation mechanism transitions from planar separation to three-dimensional conformal spacing. Dielectric spacers extend vertically and radially around semiconductor layers, utilizing the third dimension to maintain electrical isolation even when horizontal spacing between devices is reduced for higher density.
3Reliability
If dielectric spacers are formed around semiconductor layers, then electrical isolation is improved, but manufacturing process complexity increases
Solution Approach 1:
The conformal deposition process automatically forms dielectric spacers with uniform thickness around semiconductor layers, utilizing the self-aligning nature of conformal growth. This self-service approach eliminates the need for additional alignment steps and complex patterning processes that would otherwise be required to create isolation structures.
Solution Approach 2:
The formation of dielectric spacers is combined with the existing sacrificial layer formation process. The same conformal deposition technique used for creating sacrificial layers is also used to form the dielectric spacers, merging two functions into a single process step and reducing overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables further miniaturization of FETs by preventing parasitic epitaxy and maintaining electrical isolation, enhancing structural gains and reducing device area footprint.
Implementation Method 1
dielectric spacer is disposed around at least one end portion of the semiconductor layer, wherein the semiconductor layer is electrically isolated from the at least one source/drain region
Data Source
AI summary
A semiconductor device comprises a first nanosheet transistor structure, a second nanosheet transistor structure stacked on the first nanosheet transistor structure, and a semiconductor layer disposed between the first nanosheet transistor structure and the second nanosheet transistor structure. A first dielectric spacer is disposed around a first end portion of the semiconductor layer, and a second dielectric spacer disposed around a second end portion of the semiconductor layer. The second end portion of the semiconductor layer is disposed opposite the first end portion.