Multi-Layer Dielectric Stack for Reduced Contact Pad Pitch
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Solution Overview
Problem
Current embedded chip interconnect technologies face challenges in reliably connecting semiconductor devices with tight contact pad pitches due to the limitations imposed by the minimum via cover pad length, metal feature size, and gap requirements, leading to potential shorts and design constraints.
Innovation Solution
The solution involves a multi-layer dielectric stack with a first and second dielectric layer, where a first contact pad via is formed through the first dielectric layer, and a second contact pad via is formed through both dielectric layers, allowing for a second cover pad to be positioned on the top surface, thereby reducing the gap between cover pads and minimizing the contact pad pitch without increasing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a single dielectric layer with via cover pads is used, then the structure is simple, but the minimum contact pad pitch is constrained to be large (70 microns or more) due to the need for sufficient via cover pad length and gap between cover pads
Solution Approach 1:
The single dielectric layer is segmented into multiple dielectric layers (first dielectric layer and second dielectric layer). The via structure is divided into a first via through the first dielectric layer and a second via through the second dielectric layer. This segmentation allows the cover pads to be distributed across different layers, reducing the required pitch between contact pads while maintaining reliable electrical isolation.
Solution Approach 2:
The via structure transitions from a single-layer horizontal arrangement to a multi-layer vertical arrangement. The first cover pad is formed on the first dielectric layer, while the second cover pad is formed on the second dielectric layer at a different vertical level. This dimensional change allows cover pads to be positioned closer together horizontally while maintaining vertical separation for electrical isolation.
2Productivity
If the contact pad pitch is reduced to increase device density, then more I/O connections can be achieved, but shorts occur between cover pads due to insufficient gap distance
Solution Approach 1:
By stacking dielectric layers vertically, the cover pads are positioned at different vertical levels (first cover pad on first dielectric layer, second cover pad on second dielectric layer). This vertical separation provides electrical isolation while allowing horizontal pitch reduction, thereby increasing device density without causing shorts between adjacent cover pads.
Solution Approach 2:
The interconnect structure is segmented into multiple dielectric layers with各自的 via and cover pad structures. This segmentation allows independent optimization of each layer's features, enabling reduced pitch while maintaining sufficient isolation distances through the vertical stacking arrangement.
3Reliability
If the via cover pad length is increased to ensure reliable connection, then connection reliability improves, but the minimum contact pad pitch increases due to the larger space required
Solution Approach 1:
The via connection structure utilizes vertical stacking of multiple dielectric layers and vias. The first via through the first dielectric layer and the second via through the second dielectric layer provide extended connection paths vertically, allowing sufficient connection reliability while reducing the horizontal pitch between contact pads.
Solution Approach 2:
The multi-layer via structure nests vias and cover pads within stacked dielectric layers. The first via and first cover pad are nested within the first dielectric layer, while the second via and second cover pad are nested within the second dielectric layer, creating a compact vertical arrangement that reduces horizontal space requirements.
Data Source
AI summary
An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first contact pad and a second contact pad thereon and being free of an intervening contact pad therebetween, a first dielectric layer coupled to the electronic chip over the first and second contact pads, and a second dielectric layer coupled to the first dielectric layer such that a dielectric layer boundary is formed therebetween. The first dielectric layer has a first contact pad via formed therethrough at a first location corresponding to the first contact pad and extending down thereto. The second dielectric layer has a second contact pad via formed therethrough at a second location corresponding to the second contact pad and extending down thereto such that a second contact pad multi-layer via is formed through the first and second dielectric layers at the second location corresponding to the second contact pad.