Dielectric Stack Under Gate for Backside Trench Alignment
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the misalignment of backside contact trenches during backside processing, which can lead to shorts with the gate, causing device failure due to the lack of a reliable CMP stop and etch stop during substrate removal.
Innovation Solution
Incorporation of a dielectric stack under the gate, comprising alternating layers of high-k dielectric and gate spacer material, serving as a CMP stop and etch stop to prevent misalignment and shorts, and providing a hard mask for precise backside contact patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If substrate removal is performed during backside processing, then productivity is improved by enabling backside power distribution network fabrication, but manufacturing precision deteriorates due to misalignment of backside contact trenches
Solution Approach 1:
A dielectric stack is formed under the gate structure before backside contact trench etching. This pre-formed stack serves as a reference feature that enables precise alignment of subsequent trenches, ensuring accurate positioning of backside contacts relative to the gate without compromising productivity
Solution Approach 2:
The dielectric stack acts as an intermediary reference structure between the gate and the backside contact trenches. By providing a visible and measurable feature at the substrate level, it mediates the alignment process, allowing trenches to be precisely positioned relative to the gate through the intermediate reference provided by the stack
2Ease of manufacture
If no CMP stop layer is present during substrate removal, then ease of manufacture is improved by simplifying the structure, but reliability deteriorates due to inability to prevent over-etching and misalignment
Solution Approach 1:
The dielectric stack is formed in advance with materials having distinct etch selectivity and CMP stop properties. This preliminary structure serves as a built-in protection mechanism that prevents over-etching and misalignment during subsequent processing steps, ensuring device reliability without adding complex process steps
Solution Approach 2:
The dielectric stack serves as an intermediary protective layer between the substrate removal process and the sensitive gate structure. It mediates the etching and CMP processes by providing a stop layer that prevents damage to underlying structures while enabling precise alignment of backside contacts
Data Source
AI summary
A chip includes a first epitaxial (epi) layer, a second epi layer, a gate between the first epi layer and the second epi layer, and one or more channels coupled between the first epi layer and the second epi layer, wherein the one or more channels pass through the gate. The chip also includes a dielectric stack under the gate, the dielectric stack including one or more first dielectric layers and one or more second dielectric layers.