Thin Dielectric Layer Strain Energy Control for PCB Capacitance

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Solution Overview

Problem

The existing methods for producing dielectric layer-equipped printed wiring boards face challenges with brittle dielectric layers, which can be damaged during production and result in variations in thickness, leading to capacitance discrepancies in embedded capacitors.

Innovation Solution

A method involving a metal clad laminate with a dielectric layer of 30 μm or less and a strain energy at break of 1.8 MJ or less, where the dielectric layer is formed without reinforcing materials and contains dielectric particles to enhance capacitance while minimizing thickness variations and damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the dielectric layer is made thin to reduce capacitor size and increase density, then the capacitance per unit area increases, but the dielectric layer becomes more brittle and prone to damage during production

Engineering Contradiction:
Improvethickness uniformityVSAvoiddielectric layer integrity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent changes the physical-chemical parameters of the dielectric layer by controlling the strain energy at break to be 1.8 MJ or less. This parameter optimization allows the dielectric layer to maintain both thinness (30 μm or less) for high capacitance density and sufficient flexibility to resist damage during production processes

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent creates a composite structure by incorporating dielectric particles into the dielectric layer matrix. This composite approach enhances the capacitance while the specific strain energy control ensures the composite material maintains adequate toughness and resistance to production-induced damage

Inventive Principle:
Principle #40Composite materials

2Manufacturing precision

If the dielectric layer thickness is reduced to achieve finer circuit structures, then the number of surface mounted components can be reduced, but the capacitance value becomes highly sensitive to thickness variations

Engineering Contradiction:
Improvethickness controlVSAvoidcapacitance accuracy
Core Design Contradiction:
Manufacturing precisionVSMeasurement precision

Solution Approach 1:

By establishing the strain energy at break as a critical control parameter (≤1.8 MJ), the patent creates a dielectric layer that is less sensitive to thickness variations. This parameter control reduces the coupling between thickness deviations and capacitance value deviations, improving capacitance accuracy even in thin layers

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces a feedback mechanism through strain energy measurement and control. By monitoring and controlling the strain energy at break during dielectric layer formation, the process ensures consistent capacitance values despite natural variations in thickness, effectively decoupling the two parameters

Inventive Principle:
Principle #23Feedback

3Ease of manufacture

If conventional dielectric layers are used in the B stage, then the production process can proceed with standard materials, but the dielectric layers exhibit large thickness variations due to support member undulations

Engineering Contradiction:
Improveprocess simplicityVSAvoiddielectric layer thickness uniformity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent changes the material state parameter from conventional B-stage dielectric layers to a specifically controlled dielectric layer with strain energy at break of 1.8 MJ or less. This parameter change makes the dielectric layer inherently more resistant to thickness variations caused by support member undulations, achieving both ease of manufacture and high precision

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10342143B2Production method for printed wiring board having dielectric layer
Publication Date: 2019.07.02 MITSUI MINING & SMELTING CO LTD
  • US10342143B2 patent drawing
  • US10342143B2 patent drawing
  • US10342143B2 patent drawing

AI summary

A production method includes: preparing a metal clad laminate including a dielectric layer≤30 μm thick, a first metal foil on a first surface of the dielectric layer, a second metal foil on a second surface of the dielectric layer, first and second carriers on the metal foil via a releasable layer; arranging the pair of metal clad laminates on a resin substrate so the first carrier of each metal clad laminate faces the resin substrate on each surface of the resin substrate; releasing the second carrier from a laminated member to expose the second metal foil; forming a pattern on the second metal foil; arranging an insulating layer on the pattern and arranging a metal layer on the insulating layer; and separating the first carrier and the first metal foil from each other. The dielectric layer has a strain energy at break of 1.8 MJ or less.