Dielectric Stress Compensation in IC Interconnect Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits face variations in transistor performance due to stress imparted by package structures, which can counter or add to the stress provided by stressors, leading to non-uniform carrier mobility and drive current variations across the chip.
Innovation Solution
The implementation of selectively implanted stress-setting dopants in the dielectric layer over metal interconnect layers allows for tailored stress profiles that counteract the stress effects from package structures, ensuring consistent transistor performance across the integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stressors are formed to improve carrier mobility, then transistor performance is improved, but stress variations from package structures cause non-uniform performance across the chip
Solution Approach 1:
The patent applies preliminary anti-action by forming compensation stressors that generate stress opposite to the harmful stress from package structures. The compensation stressors are specifically designed to counteract the stress variations before they can degrade transistor performance, thereby pre-neutralizing the harmful effects and ensuring uniform carrier mobility across the chip.
Solution Approach 2:
The patent implements local quality by positioning compensation stressors at specific locations where harmful stress from package structures is most pronounced. Rather than applying uniform stress compensation across the entire chip, the compensation stressors are strategically placed to address local stress variations, providing targeted stress counteraction where needed most to maintain consistent transistor performance.
2Reliability
If package structures are formed to encapsulate the integrated circuit, then device protection is achieved, but stress is imparted to the substrate causing performance variations
Solution Approach 1:
The patent applies the counterweight principle by introducing compensation stressors that generate stress opposing the harmful stress from package structures. These compensation stressors act as a counterbalancing force, neutralizing the stress imparted by package encapsulation and preventing it from causing performance variations in the integrated circuit devices.
Solution Approach 2:
The patent utilizes parameter changes by adjusting the stress characteristics of the dielectric layer through selective dopant implantation. By modifying the dopant concentration and distribution in specific regions of the dielectric layer, the stress state of the layer is changed to compensate for the stress from package structures, thereby maintaining consistent transistor performance despite package-induced stress.
3Productivity
If stressors are used to improve carrier mobility, then drive current increases, but threshold voltage variations occur due to stress non-uniformity
Solution Approach 1:
The patent implements local quality by selectively implanting dopants in specific regions of the dielectric layer to create localized stress compensation zones. This targeted approach allows drive current enhancement in regions where it is needed while maintaining uniform threshold voltage by compensating for stress variations locally, rather than applying uniform stress modification across the entire device.
Solution Approach 2:
The patent applies parameter changes by modifying the dopant concentration and distribution in the dielectric layer to adjust the stress state. By changing the dopant parameters (concentration, depth, spatial distribution), the stress-induced threshold voltage variations are compensated while preserving the beneficial drive current enhancement from the stressors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively neutralizes the stress effects from package structures, maintaining consistent carrier mobility and drive current across the integrated circuit, thereby enhancing overall performance and reliability.
Implementation Method 1
The dielectric layer includes selective regions of implanted stress-setting dopants to provide different stress profiles in the dielectric layer
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An integrated circuit includes a dielectric layer located over one or more metal interconnect layers. The dielectric layer includes selective regions of implanted stress-setting dopants to provide different stress profiles in the dielectric layer to counteract the stress imparted from package structures. Accordingly, the effect of the stress imparted by package structures in a substrate can be negated by the placement of stress-setting dopants in selective areas of the dielectric layer.