Dielectric Substrate Packaging for Thermally Isolated Power Dies

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Solution Overview

Problem

Conventional packaged electronic devices do not adequately isolate the power semiconductor die from the primary thermal interface, leading to potential short circuits and reduced reliability, especially in high-voltage applications.

Innovation Solution

The packaged electronic devices incorporate a dielectric substrate with a thermally conductive adhesion layer, such as a metal braze layer, to electrically isolate the power semiconductor die from the primary thermal interface, while maintaining effective heat dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If the power semiconductor die is directly attached to the metal submount for heat dissipation, then heat dissipation efficiency is improved, but electrical isolation is compromised leading to potential short circuits

Engineering Contradiction:
Improveheat dissipation efficiencyVSAvoidelectrical isolation
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent introduces a dielectric substrate as an intermediary component between the power semiconductor die and the metal submount. This dielectric substrate provides both thermal conduction path and electrical isolation, serving as a mediator that resolves the contradiction between heat dissipation efficiency and electrical isolation. The dielectric substrate allows heat to flow from the die to the submount while preventing electrical short circuits.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs composite material structure consisting of dielectric substrate with thermally conductive adhesive layers. This composite structure combines the electrical insulation properties of dielectric materials with the thermal conduction properties of thermally conductive adhesives, achieving both electrical isolation and effective heat dissipation simultaneously.

Inventive Principle:
Principle #40Composite materials

2Reliability

If a dielectric substrate with thermally conductive adhesive layers is introduced to provide electrical isolation, then electrical isolation and reliability are improved, but device complexity increases

Engineering Contradiction:
Improveelectrical isolationVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple functions into the dielectric substrate component. The dielectric substrate simultaneously provides electrical isolation, thermal conduction, and mechanical support functions. By combining these functions into a single integrated component rather than separate layers, the structure complexity is minimized while achieving the desired electrical isolation and heat dissipation performance.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enhances the reliability and current carrying capacity of packaged electronic devices by preventing short circuits and ensuring reliable electrical isolation, even in high-voltage applications, without significant additional cost.

Implementation Method 1

a thermally conductive adhesion layer on an upper side of the dielectric substrate

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

the thermally conductive adhesion layer comprises a metal braze layer. The metal braze layer may, for example, be directly attached to the ceramic substrate and to the lower side of the lead frame

Methodology Applied
Scientific EffectBrazing: Brazing

Data Source

PatentUS20250149432A1Packaged electronic devices having dielectric substrates with thermally conductive adhesive layers
Publication Date: 2025.05.08 WOLFSPEED INC
  • US20250149432A1 patent drawing
  • US20250149432A1 patent drawing
  • US20250149432A1 patent drawing

AI summary

A packaged electronic device comprises a power semiconductor die that comprises a first terminal and a second terminal, a lead frame comprising a lower side and an upper side that comprises a die pad region, a first lead and a second lead, wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame, a dielectric substrate, and a thermally conductive adhesion layer on an upper side of the dielectric substrate. The power semiconductor die is on the die pad region of the lead frame and the lead frame is on an upper side of the thermally conductive adhesion layer