3D Printed Dielectric Support for Stacked Semiconductor Chip Package
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating multiple chips into a single package with smaller size, higher speed, greater bandwidth, and high energy efficiency, as existing packaging methods struggle to efficiently stack and connect semiconductor dies while maintaining a compact footprint and reducing voids and electrical connection lengths.
Innovation Solution
A 3D printing process is used to form dielectric structures with adhesive properties, allowing for flexible support configurations and sufficient gaps to facilitate the stacking of top semiconductor dies over bottom dies, with conductive pillars providing short electrical paths and an insulating encapsulant filling all spaces, enabling a single encapsulation process and compact chip package design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging methods are used to integrate multiple chips, then the packaging can accommodate multiple semiconductor dies, but the footprint size becomes larger and voids are formed between layers
Solution Approach 1:
The patent transitions from conventional planar packaging to three-dimensional die stacking, where semiconductor dies are arranged vertically in multiple layers rather than horizontally. This dimensional change enables compact integration of multiple chips while minimizing footprint and eliminating voids through direct face-to-face bonding interfaces between adjacent dies.
2Area of stationary object
If die stacking is used to integrate multiple chips, then the footprint is reduced, but the electrical connection length increases and alignment becomes difficult
Solution Approach 1:
The patent implements preliminary alignment mark formation on each semiconductor die before the stacking process. These pre-formed alignment marks enable precise registration and positioning of dies during assembly, ensuring accurate electrical connections between bonding pads of adjacent dies while maintaining short connection lengths through optimized vertical stacking geometry.
3Productivity
If multiple semiconductor dies are stacked, then integration density increases, but alignment precision and bonding accuracy become more difficult to achieve
Solution Approach 1:
The patent segments the alignment and bonding process into discrete, manageable steps with dedicated alignment marks on each die layer. This segmentation allows for incremental positioning and verification of each die stack, maintaining high alignment precision even as integration density increases through additional stacking layers.
Solution Approach 2:
The patent introduces alignment marks as intermediary features that mediate the positioning between adjacent semiconductor dies. These visible markers serve as reference points that facilitate precise alignment during the stacking process, enabling accurate bonding pad registration without requiring complex alignment mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient stacking and connection of semiconductor dies, reducing voids and electrical connection lengths, resulting in a smaller footprint and improved performance with a shorter electrical path, while maintaining the integrity of the semiconductor components.
Implementation Method 1
A 3D printing process is used to form dielectric structures with adhesive properties
Implementation Method 2
an insulating encapsulant filling all spaces
Data Source
AI summary
A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.