Dielectric Trench Fill Using In-Situ ALE Sidewall Etching
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Solution Overview
Problem
The challenge of filling narrow trenches in semiconductor devices with dielectric material without clogging at the top and creating voids or seams, while maintaining uniform distribution, is exacerbated by conventional etching methods that unevenly etch the bottom of the gap, leading to non-uniform deposition.
Innovation Solution
A method involving the deposition of a dielectric layer followed by a hydrogen plasma modification and subsequent atomic layer etching (ALE) to selectively remove the modified layer on sidewalls, ensuring uniformity and completeness of gap filling without significant bottom etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching is used to remove dielectric material clog at the top of the gap, then the top clog is removed, but the dielectric material at the bottom of the gap etches faster than the top, reducing thickness and preventing uniform distribution
Solution Approach 1:
The patent applies local quality by making the etching process selective to different locations within the gap. The etching conditions are optimized so that the top of the gap (where clog occurs) is etched preferentially while the bottom of the gap is protected from excessive etching. This spatially differentiated etching rate compensates for the non-uniform deposition, restoring uniform dielectric material distribution throughout the gap.
Solution Approach 2:
The patent changes etching parameters (such as etchant concentration, temperature, or exposure time) to achieve selective etching rates at different locations in the gap. By adjusting these parameters, the etching process is tuned to remove material faster from the top where clog occurs, while maintaining the dielectric material thickness at the bottom where excessive etching would cause problems.
2Manufacturing precision
If selective etching is implemented to limit bottom of the gap from etching at the same rate as the top, then etching selectivity is improved, but bubbles form in the dielectric material
Solution Approach 1:
The patent applies preliminary action by performing a controlled etching step before the final dielectric deposition. This preliminary etching removes potential clog material and prepares the surface, but is carefully controlled to avoid creating conditions that would lead to bubble formation during subsequent processing. The etching is stopped before excessive material removal occurs, preventing the conditions that cause bubbling.
Solution Approach 2:
The patent maintains continuity of useful action by integrating the etching step seamlessly into the overall deposition process. The etching is performed as part of a continuous cyclic process where deposition and etching alternate, allowing the system to maintain stable conditions throughout. This continuous cyclic approach prevents abrupt changes that could cause bubble formation while maintaining etching selectivity.
3Quantity of substance
If dielectric material is deposited to fill narrow trenches, then gap filling is achieved, but the deposition is prone to clog at the top before the gap is completely filled, producing void or seam in the middle
Solution Approach 1:
The patent applies periodic action by using a cyclic deposition process where dielectric material is deposited in multiple alternating layers rather than as a single continuous layer. Each deposition cycle deposits a thin layer, then an etching step selectively removes material from the top. This periodic alternation of deposition and selective etching allows the material to flow into and fill the narrow gap completely, preventing clog formation and ensuring uniform distribution throughout the gap.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves uniform dielectric filling in narrow trenches by selectively etching sidewalls, maintaining gap integrity and reducing the likelihood of voids or seams, while allowing high-temperature and high-pressure processing for efficient integration.
Implementation Method 1
A portion of the dielectric layer is modified to form a modified dielectric layer
Implementation Method 2
An atomic layer etch is performed to remove the modified dielectric layer
Implementation Method 3
A dielectric layer is deposited over the substrate within the processing chamber
Data Source
AI summary
A device includes a substrate comprising a plurality of structures and a dielectric layer. A first structure of the plurality of structures is separated from a second structure of the plurality of structures by a first distance. Each structure of the plurality of structures has an aspect ratio of about 5:1 to about 15:1. The dielectric layer is disposed on an upper surface of the substrate, a first sidewall and a second sidewall of the plurality of structures, and an upper surface of the plurality of structures. The dielectric layer has a thickness of about 1 nm to about 5 nm on the sidewalls of the plurality of structures. A method of forming a device includes depositing the dielectric layer over the substrate. A portion of the dielectric layer is modified to form a modified dielectric layer. An atomic layer etch is performed to remove the modified dielectric layer.