Dielectric Trench Isolation for Zero Diffusion Breaks
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Solution Overview
Problem
The area consumed by diffusion breaks in integrated circuit (IC) layout is significant, constraining transistor density improvements, especially in small cells like NAND logic cells, which account for a substantial proportion of chip area.
Innovation Solution
Implementing zero diffusion break (ZDB) isolations using a dielectric trench to isolate adjacent transistors, reducing the layout area by bisecting source and drain bodies within a shared trench, allowing transistors to be more closely situated and conserving valuable layout space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional diffusion breaks (DDB or SDB) are used to separate logic cells, then transistor isolation is achieved, but layout area is significantly consumed
Solution Approach 1:
The patent extracts the diffusion break function from the traditional layout structure by introducing a separate dielectric trench isolation structure. This allows the diffusion break functionality to be achieved without consuming horizontal layout area, as the isolation is provided by a vertical trench structure rather than horizontal spacing.
Solution Approach 2:
The patent transitions from horizontal diffusion break structures (occupying planar area) to a vertical dielectric trench structure. By moving the isolation mechanism to the vertical dimension (depth), the layout area consumption is eliminated while maintaining effective transistor separation.
2Productivity
If small cells like NAND logic cells are used frequently, then chip area utilization increases, but diffusion breaks at cell borders incur a relatively sizeable area cost
Solution Approach 1:
The patent removes the area-consuming diffusion break structures from the cell border regions by implementing dielectric trench isolations that provide the necessary separation without occupying horizontal layout space, thereby enabling higher density packing of small cells.
Solution Approach 2:
The patent combines the isolation function with the existing trench structure by implementing dielectric material filling in the trenches, thereby achieving both structural support and electrical isolation functions simultaneously without additional area overhead.
3Quantity of substance
If diffusion breaks are reduced to improve density, then transistor density increases, but parasitic capacitances may increase
Solution Approach 1:
The patent introduces dielectric material as an intermediary substance filling the trench structures between adjacent transistors. This dielectric intermediary provides electrical isolation that prevents parasitic capacitance formation while allowing the transistors to be positioned closer together for higher density.
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
Isolation breaks between logic cells in integrated circuit (IC) devices. A source-drain trench between adjacent channel regions includes a pair of source or drain semiconductor bodies, a first of the source or drain bodies in the source-drain trench is connected to a first of the channel regions, a second of the source or drain bodies in the source-drain trench is connected to a second of the channel regions, and a dielectric isolation is in the source-drain trench and between the pair of source or drain bodies. The dielectric isolation may include a void between layers or sidewalls of dielectric. The pair of source or drain bodies may include highly conductive, metallized layers in contact with the dielectric isolation.