Dielectric Trenches for Interposer Capacitor Area Expansion
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Solution Overview
Problem
The existing fabrication techniques for decoupling capacitors and conductive features in interposers are limited by the placement and area constraints of conductive paths, which restrict the size and placement of capacitor plates, and there is a need for alternative methods to achieve high capacitance without leakage and efficient chemical mechanical polishing processes.
Innovation Solution
The use of dielectric trenches to insulate conductive paths from capacitor plates, allowing for larger capacitor plate areas, and the application of tantalum pentoxide as a high dielectric constant material, along with chemical mechanical polishing techniques that pattern layers to increase protruding features for faster polishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive paths are used to connect power and ground terminals, then electrical connectivity is achieved, but the placement and area of capacitor plates are restricted
Solution Approach 1:
The conductive path layer is segmented by forming dielectric trenches that divide the continuous metal layer into isolated regions. This segmentation allows capacitor plates to be formed in areas that would otherwise be occupied by conductive paths, thereby increasing the effective capacitor plate area while maintaining necessary electrical connectivity through the segmented conductive regions.
Solution Approach 2:
Dielectric trenches are formed to extract or remove the dielectric material from specific regions, creating isolated islands of conductive material. This extraction process separates conductive paths from capacitor plate areas, allowing capacitor plates to occupy spaces that would otherwise be constrained by continuous conductive paths.
2Reliability
If capacitor plates are placed close to power and ground inputs, then parasitic inductance is reduced, but the area available for capacitor formation is limited
Solution Approach 1:
The invention utilizes the vertical dimension by forming dielectric trenches that extend through multiple layers, creating three-dimensional isolation structures. This allows capacitor plates to be positioned in previously unavailable vertical spaces and enables stacking arrangements, effectively increasing capacitor area without expanding the planar footprint and maintaining proximity to power and ground inputs.
3Ease of manufacture
If standard CMP processes are used, then fabrication is simple, but polishing time is excessive for thick dielectric layers
Solution Approach 1:
Dielectric trenches are formed preliminarily before the final CMP process, creating physical discontinuities and reducing the effective thickness of dielectric material that requires polishing. This preliminary action removes excess dielectric material in trench regions, thereby reducing the overall polishing time required while maintaining the simplicity of the CMP process for the remaining areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of interposers with larger capacitor plates, improved capacitance, and reduced fabrication time, suitable for both semiconductor and ceramic substrates, while also facilitating the creation of ground and power planes and other conductive features.
Implementation Method 1
the application of tantalum pentoxide as a high dielectric constant material
Implementation Method 2
chemical mechanical polishing techniques that pattern layers to increase protruding features for faster polishing
Data Source
AI summary
A portion of a conductive layer (310, 910) provides a capacitor electrode (310.0, 910.0). Dielectric trenches (410, 414, 510) are formed in the conductive layer to insulate the capacitor electrode from those portions of the conductive layer which are used for conductive paths passing through the electrode but insulated from the electrode. Capacitor dielectric (320) can be formed by anodizing tantalum while a nickel layer (314) protects an underlying copper (310) from the anodizing solution. This protection allows the tantalum layer to be made thin to obtain large capacitance. Chemical mechanical polishing of a layer (610) is made faster, and hence possibly less expensive, by first patterning the layer photolithographically to form, and/or increase in height, upward protrusions of this layer.