3D Memory Dielectric Wall Support Structures
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in reducing lateral connection resistance of word lines, which affects the performance and efficiency of memory arrays.
Innovation Solution
The implementation of dielectric wall support structures in staircase regions within the memory device, formed through a method involving alternating stacks of insulating and sacrificial layers, dielectric cavity fill materials, and the replacement of sacrificial layers with conductive materials, reduces lateral connection resistance by creating a structured architecture that minimizes electrical resistance across the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory device architecture is used, then device structure is simple, but lateral connection resistance of word lines is high
Solution Approach 1:
The device is segmented into multiple memory array regions separated by dielectric wall structures. These dielectric walls create distinct regions while providing pathways for word line connections, effectively segmenting the device to reduce lateral connection resistance without requiring a complete redesign of the entire structure.
Solution Approach 2:
The patent introduces vertical stacking of memory array regions across multiple levels. By transitioning from a two-dimensional layout to a three-dimensional stacked architecture, word lines can connect to memory cells through vertical pathways rather than relying solely on lateral connections, thereby reducing lateral connection resistance.
2Area of stationary object
If memory array regions are closely spaced, then device area is reduced, but lateral connection resistance increases
Solution Approach 1:
By stacking memory array regions vertically across multiple levels, the patent reduces the lateral footprint of the device while maintaining adequate spacing between regions. The vertical dimension provides additional pathways for word line connections, allowing closely spaced regions without increasing lateral connection resistance.
Solution Approach 2:
The dielectric wall structures serve multiple functions: they separate memory array regions, provide mechanical support, and facilitate word line connections. This multi-functionality allows regions to be closely spaced while maintaining low lateral connection resistance through the integrated design of the dielectric walls.
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located between line trenches, a first memory array region and a second memory array region, and a pair of dielectric wall structures located between the first line trench and the second line trench and between the memory array regions. Each layer within the alternating stack continuously extends between the first memory array region and the second memory array region in a connection region. The electrically conductive layers of the alternating stack have lateral extents that decrease with a distance from the substrate in a staircase region. Dielectric material plates interlaced with insulating plates or insulating layers are provided between the dielectric wall structures.