Dielectric Wall CFET Layout for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, the integration density of electronic components increases, but this leads to challenges such as increased parasitic capacitance between source/drain contacts and gate structures, which affects device performance and efficiency.
Innovation Solution
The implementation of complementary field-effect transistors (FETs) with dielectric walls between adjacent nanostructures, where the gate structures are formed above the dielectric walls, reducing the parasitic capacitance by having a majority of the source/drain contact extend along the dielectric wall instead of the gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If source/drain contacts are positioned adjacent to gate structures for compact layout, then integration density is improved, but parasitic capacitance between source/drain contacts and gate structures increases
Solution Approach 1:
A dielectric wall is introduced as an intermediary structure between the source/drain contact and the gate structure. This dielectric wall physically separates the two conductive elements, preventing direct electrical interaction and reducing parasitic capacitance while allowing the contact to remain in close proximity to the gate for high integration density.
Solution Approach 2:
The space between the source/drain contact and gate structure is segmented by introducing a dielectric wall that divides the region into distinct zones. This segmentation creates electrical isolation while maintaining spatial compactness, allowing the contact to be positioned close to the gate without direct capacitive coupling.
2Productivity
If feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision and control over parasitic effects become more difficult
Solution Approach 1:
The dielectric wall is formed in advance during the fabrication process, before the source/drain contact and gate structure are fully assembled. This preliminary action ensures that the isolating structure is already in place to prevent parasitic capacitance formation, making the subsequent assembly processes more tolerant and easier to control with reduced feature sizes.
Solution Approach 2:
The dielectric wall serves as a pre-positioned intermediary that facilitates precise positioning of miniaturized components. By having this isolating structure in place beforehand, manufacturers can more accurately control the placement of source/drain contacts and gate structures at reduced feature sizes without suffering from uncontrolled parasitic effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces parasitic capacitance, enhancing the performance and efficiency of semiconductor devices by minimizing the overlap between source/drain contacts and gate electrodes, thereby improving the overall functionality of the devices.
Implementation Method 1
reducing the parasitic capacitance by having a majority of the source/drain contact extend along the dielectric wall instead of along the gate structure
Data Source
AI summary
In an embodiment, a device includes: a dielectric wall; nanostructures abutting the dielectric wall; a lower source/drain region adjoining a lower subset of the nanostructures; an upper source/drain region adjoining an upper subset of the nanostructures, the upper source/drain region oppositely doped from the lower source/drain region; and a shared source/drain contact contacting the upper source/drain region and the lower source/drain region, the shared source/drain contact extending into the dielectric wall.