Dielectric Wall Mitigates Dopant Diffusion in Semiconductor Devices
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Solution Overview
Problem
The short channel effect in semiconductor devices, characterized by increased lateral diffusion of dopants in source and drain regions, leads to higher leakage current and reduced carrier mobility, which degrades device performance, especially in scaled-down devices where conventional methods like ultra shallow junctions and low-energy light doped regions are insufficient.
Innovation Solution
The implementation of dielectric walls, vertically aligned between the source and drain regions and the gate, which block lateral diffusion of dopants, thereby reducing the short channel effect and maintaining low resistance values, allowing for improved carrier mobility and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher doping concentration and higher impurity activation temperature are used to reduce resistance in source and drain regions, then resistance value decreases, but lateral diffusion of dopants increases causing drain induction barrier lower effect and leakage current increase
Solution Approach 1:
The source and drain regions are segmented into multiple doping zones with different doping concentrations. The method uses multi-step ion implantation to create a first doped region with higher doping concentration and a second doped region with lower doping concentration, allowing each zone to serve different functions in reducing resistance while controlling lateral diffusion.
Solution Approach 2:
Different regions of the source and drain are given different doping concentrations according to their specific functional requirements. The first doped region has higher doping concentration for low resistance, while the second doped region has lower doping concentration to suppress lateral diffusion and reduce drain induction barrier lower effect.
2Object-generated harmful factors
If conventional methods like ultra shallow junction and low-energy light doped regions are used, then lateral diffusion is reduced, but these methods become insufficient as device dimension is scaled down
Solution Approach 1:
The patent employs a composite doping structure combining multiple doping techniques and concentrations. By integrating first and second ion implantation steps with different energy levels and doping concentrations, the method creates a composite doped region that simultaneously achieves low lateral diffusion and maintains device performance at scaled dimensions.
3Object-generated harmful factors
If doping concentration in source and drain doped regions is decreased to prevent lateral diffusion, then lateral diffusion is reduced, but resistance value increases and carrier mobility decreases
Solution Approach 1:
The doping structure is segmented into multiple regions with different concentrations. The first doped region maintains higher doping concentration to ensure low resistance and good carrier mobility, while the second doped region uses lower doping concentration to prevent lateral diffusion, allowing both requirements to be satisfied simultaneously in different zones.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dielectric walls effectively mitigate the short channel effect, reducing leakage current and channel punch-through while maintaining low resistance values, enabling higher performance and faster operation of semiconductor devices with reduced junction capacitance and leakage current.
Implementation Method 1
the higher doping concentration and the higher impurity activation temperature (annealing temperature) may cause lateral diffusion of dopants in the source and drain regions
Implementation Method 2
a higher doping concentration and a higher impurity activation temperature (annealing temperature) are required
Data Source
AI summary
Disclosed is a semiconductor device and a method for fabricating the semiconductor device. The method for fabricating the semiconductor device comprises steps of: forming a side cliff in a substrate in accordance with a gate mask pattern, the side cliff being substantially vertical to a substrate surface; forming a dielectric layer on the substrate that comprises the side cliff; etching the dielectric layer to have the dielectric layer left only on the side cliff, as a dielectric wall; and burying the side cliff by a substrate growth, the burying is performed up to a level higher than the upper end of the dielectric wall.