Dielectric-Wall GAA Nanosheets for Leakage and Corner Control
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down semiconductor integrated circuits due to issues such as increased leakage and reduced channel control, particularly in multi-gate devices like gate-all-around (GAA) transistors, which affect device performance and efficiency.
Innovation Solution
The method involves forming a semiconductor device with a gate-all-around (GAA) structure using a semiconductor stack with alternating SiGe and Si layers, patterned to create nanosheet stacks and dielectric walls, and subsequent formation of strained layers and gate structures to enhance channel control and reduce leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost are improved, but leakage increases and channel control deteriorates
Solution Approach 1:
The gate structure completely surrounds the channel region in a nested configuration, with the gate electrode wrapping around the nanosheet channel from all sides. This three-dimensional gate-all-around structure provides comprehensive control over the channel, effectively suppressing leakage currents while maintaining scaled-down dimensions for high functional density.
Solution Approach 2:
The invention transitions from planar two-dimensional gate control to three-dimensional gate-all-around control by extending the gate structure into the vertical dimension and wrapping it around the channel. This dimensional change enables superior electrostatic control and leakage suppression at scaled geometries.
2Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost are improved, but channel control deteriorates
Solution Approach 1:
The gate electrode is nested around the channel region, providing control from all directions including top, bottom, and sidewalls. This complete surrounding control ensures excellent electrostatic management of the channel even at reduced geometry sizes, maintaining ease of operation despite scaling.
Solution Approach 2:
The gate structure employs composite materials including high-k dielectric layers and conductive electrode materials, which enhance gate control capability. The multi-material construction improves electrostatic control and enables effective channel management at scaled dimensions.
3Ease of operation
If multi-gate device structure is used to improve channel control, then device performance is enhanced, but device complexity increases
Solution Approach 1:
The channel region is segmented into multiple nanosheets stacked vertically, with the gate structure wrapping around each nanosheet. This segmentation into discrete nanosheet channels provides superior control while the repetitive stacked structure enables scalable manufacturing, balancing performance enhancement with manufacturing feasibility.
Solution Approach 2:
The gate-all-around structure serves multiple functions simultaneously: it controls the channel, suppresses leakage, provides mechanical support, and enables scalable fabrication. This multi-functionality reduces overall device complexity by consolidating multiple roles into a single integrated structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance by increasing effective channel width, reducing leakage, and mitigating weak corner turn-on effects, leading to enhanced semiconductor device efficiency and reliability.
Implementation Method 1
forming a semiconductor device with a gate-all-around (GAA) structure using a semiconductor stack with alternating SiGe and Si layers, patterned to create nanosheet stacks
Implementation Method 2
subsequent formation of strained layers and gate structures to enhance channel control and reduce leakage
Data Source
AI summary
A semiconductor device includes a substrate, a first stack of semiconductor nanosheets, a second stack of semiconductor nanosheets, a gate structure and a first dielectric wall. The substrate includes a first fin and a second fin. The first stack of semiconductor nanosheets is disposed on the first fin. The second stack of semiconductor nanosheets is disposed on the second fin. The gate structure wraps the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. The first dielectric wall is disposed between the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. The first dielectric wall includes at least one neck portion between adjacent two semiconductor nanosheets of the first stack.