Dielectric Wall and Inner Spacer Layout for Scaled GAA Transistors
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Solution Overview
Problem
The integration of gate-all-around (GAA) transistor devices in semiconductor manufacturing is challenging due to the complexity of forming the gate structure around the nanowire, which hinders further scaling and performance improvements.
Innovation Solution
A semiconductor structure is formed using self-aligned dielectric walls and fin spacer layers to cut the final gate stack into segments, with H-shaped or stair-shaped inner spacer layers to protect the source/drain features during etching, facilitating the scaling down of the device and improving manufacturing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional GAA device fabrication methods are used, then gate control is improved and short-channel effects are reduced, but manufacturing complexity increases and integration around nanowires becomes challenging
Solution Approach 1:
The fabrication process is divided into distinct stages: forming sacrificial nanowire structures, depositing gate materials, removing sacrificial material, and forming final gate structures. This segmentation allows each step to be optimized independently, reducing overall fabrication complexity while maintaining gate-all-around control
Solution Approach 2:
Sacrificial nanowire structures are formed in advance before the actual gate structures are created. These preliminary structures serve as templates that guide subsequent fabrication steps, making the integration of gate features around nanowires more manageable and less complex
2Productivity
If device dimensions are scaled down to improve production efficiency and lower costs, then manufacturing productivity increases, but process complexity increases
Solution Approach 1:
The fabrication process utilizes self-aligned techniques where previously formed structures automatically serve as alignment references for subsequent steps. This self-service approach eliminates the need for additional complex alignment processes, enabling scaling down without proportionally increasing process complexity
Solution Approach 2:
The same fabrication process steps are used to create multiple features simultaneously (nanowires, gates, spacers), allowing a single process sequence to accomplish what would otherwise require multiple separate processes, thereby maintaining productivity while scaling down dimensions
Data Source
AI summary
A semiconductor structure includes a first dielectric wall, a first set of nanostructures and a second dielectric wall sequentially arranged in a first horizontal direction. A first gate electrode layer wraps around the first set of nanostructures. A source/drain feature adjoins the first set of nanostructures and is sandwiched between the first dielectric wall and the second dielectric wall. An inner spacer layer is interposed between the first gate electrode layer and the source/drain feature and between the first set of nanostructures. In a plan view, a first dimension of the inner spacer layer in the first horizontal direction is greater than a second dimension of the source/drain feature in the first horizontal direction.