Dielectric Wall Gate Layout for Overlay-Stable Nanosheet FETs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in downscaling device design and fabrication, particularly in achieving optimal cell height and contacted poly pitch (CPP) scaling due to issues like overlay shift and variation in critical dimension (CD) during photolithography processes.
Innovation Solution
The introduction of dielectric walls that separate metal gate structures prior to their formation, which helps mitigate overlay shift and CD variation, allowing for a significant reduction in cell height by approximately 65% to 75%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography processes are used to form metal gate structures, then device fabrication can proceed, but overlay shift and critical dimension variation occur leading to poor manufacturing precision
Solution Approach 1:
The patent introduces dielectric walls that physically segment and separate adjacent metal gate structures during fabrication. This segmentation prevents overlay shift between adjacent gates by providing a physical barrier that defines precise boundaries, thereby improving manufacturing precision and reducing CD variation in multi-gate devices
Solution Approach 2:
The dielectric wall acts as an intermediary structure between adjacent metal gate electrodes. This intermediary element provides a stable reference plane that mediates the positioning of adjacent gates, eliminating direct overlay requirements between gates and reducing photolithography-induced dimensional variation
2Productivity
If cell height is reduced to increase device density, then productivity improves, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent transitions from two-dimensional planar gate structures to three-dimensional multi-gate structures (FinFET or GAA) with dielectric walls providing vertical separation. This dimensional change allows increased device density through vertical stacking while the dielectric walls maintain precise dimensional control by providing physical boundaries that are independent of photolithography resolution limits
Data Source
AI summary
A semiconductor structure includes a first dielectric wall over a substrate, and two metal gate structures disposed at two sides of the first dielectric wall. Each of the metal gate structures includes a plurality of nanosheets stacked over the substrate and separated from each other, a high-k gate dielectric layer covering each of the nanosheets, and a metal layer covering and over the plurality of nanosheets and the high-k gate dielectric layer. The high-k gate dielectric layer of each metal gate structure is disposed between the metal layer of each metal gate structure and the first dielectric wall.