Dielet Design Techniques for Multi-Tier IC Interconnects
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Solution Overview
Problem
Conventional circuit designs face challenges in implementing electrical connections between on-chip circuit components in three-dimensional space due to multi-tier layering and multi-chip implementations, requiring improved physical design methodologies for multi-dielet chip technologies.
Innovation Solution
The implementation of dielet design schemes and techniques that utilize unified database methodologies for multi-dielet chip designs, incorporating inter-dielet ports with 3D geometric position information and inter-tier vias to facilitate electrical connections across physically different dies, optimizing design metrics such as delay, power, area, and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-tier layering and multi-chip implementations are used, then circuit functionality and integration are improved, but physical design implementation of electrical connections becomes difficult
Solution Approach 1:
The patent segments the physical design into modular components: dielet ports are divided into source and sink ports, and electrical connections are segmented into via holes, fill structures, and conductive paths. This segmentation allows complex multi-tier connections to be designed and optimized independently, reducing overall design complexity while maintaining functionality.
Solution Approach 2:
The patent introduces intermediary structures including via holes as connectors between tiers, and dielet ports as intermediaries between circuit components. These intermediaries simplify the connection process by providing standardized interfaces that ease the integration of multi-tier layering and multi-chip implementations.
2Adaptability or versatility
If electrical connections are implemented in three-dimensional space, then connectivity is improved, but design and implementation difficulty increases
Solution Approach 1:
The patent transitions from traditional two-dimensional PCB routing to three-dimensional interconnect architecture by introducing via holes that penetrate multiple layers. This dimensional change enables vertical interconnections between tiers while maintaining standardized design processes through dielet port definitions and automated routing tools.
Solution Approach 2:
The patent performs preliminary actions by pre-defining dielet ports with source and sink designations before routing begins. This preliminary structuring of connection points enables automated design tools to efficiently generate three-dimensional electrical connections without manual intervention, reducing implementation difficulty.
3Productivity
If unified database methodologies are used for multi-dielet design, then design optimization is improved, but system complexity increases
Solution Approach 1:
The patent creates a universal dielet port interface that serves multiple functions: defining electrical connections, specifying geometric positions, and enabling automated routing. This multi-functional approach consolidates multiple design tasks into a unified database methodology, improving optimization efficiency while managing system complexity through standardization.
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit (IC) having a design that is severable into multiple sub-circuits having input-output (IO) ports. The integrated circuit (IC) may include multiple physical electrical connections that are adapted to electrically interconnect the IO ports of the multiple sub-circuits to operate as the IC, and the IO ports have three-dimensional (3D) geometric position information associated therewith.