Network Interface DIF Engine Offloads Processor Burden
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Solution Overview
Problem
The complexity of adding, removing, and verifying data integrity fields (DIFs) in data transfer operations between storage initiators and targets complicates software and increases computational and memory bandwidth burdens on processors, particularly in high-speed network environments like InfiniBand and Fibre Channel networks.
Innovation Solution
The integration of a DIF engine within network interface circuitry in channel adapters offloads DIF-related operations, enabling automatic addition, stripping, and verification of DIFs during I/O data transfers, allowing transparent communication regardless of DIF support by initiators or targets, and supporting multiple DIF types and protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DIF operations (adding, removing, verifying) are performed in software on the processor, then data integrity can be ensured, but processor computational burden and memory bandwidth consumption increase significantly
Solution Approach 1:
The patent extracts DIF operations from the processor software and implements them in dedicated hardware circuitry within the network interface adapter. The DIF engine includes separate functional units for adding DIF fields to data blocks, removing DIF fields, and verifying DIF integrity, thereby offloading these computationally intensive operations from the general-purpose processor to specialized hardware circuits that can handle them efficiently without consuming processor cycles or memory bandwidth.
2Adaptability or versatility
If DIF operations are handled in software, then protocol compliance is achieved, but memory bandwidth burden on the processor increases
Solution Approach 1:
The patent introduces a DIF engine as an intermediary hardware component between the processor and the network interface. This DIF engine acts as a mediator that handles all DIF-related operations locally within the network interface adapter, including adding DIF fields to outgoing data blocks, removing DIF fields from incoming data blocks, and verifying DIF integrity. By placing this intermediary hardware layer at the network interface level, the system achieves protocol compliance while preventing memory bandwidth consumption associated with software-based DIF processing.
3Productivity
If DIF support is implemented in hardware within network interface circuitry, then processor burden is reduced, but device complexity in the network interface increases
Solution Approach 1:
The patent segments the DIF processing functionality into distinct modular hardware components within the network interface adapter. The DIF engine is divided into separate functional units: a DIF adding unit that appends DIF fields to data blocks, a DIF removing unit that strips DIF fields from received data, and a DIF verifying unit that checks data integrity using stored DIF values. This segmentation allows each component to be optimized independently and simplifies the overall integration into the network interface circuitry, managing complexity through functional decomposition.
Data Source
AI summary
A network communication device includes a host interface, which is coupled to communicate with a host processor, having a memory, so as to receive a work request to convey one or more data blocks over a network. The work request specifies a memory region of a given data size, and at least one data integrity field (DIF), having a given field size, is associated with the data blocks. Network interface circuitry is configured to execute an input/output (I/O) data transfer operation responsively to the work request so as to transfer to or from the memory a quantity of data that differs from the data size of the memory region by a multiple of the field size, while adding the at least one DIF to the transferred data or removing the at least one DIF from the transferred data.