Differential Amplifier Over-Voltage Protection Circuit
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Solution Overview
Problem
High voltage operational amplifiers face issues with over-voltage protection, leading to transient response degradation, large parasitic currents, and input errors due to excessive reverse bias voltage and parasitic capacitance charging, especially in common-drain-common-base topologies, which limit the use of high-performance transistors with lower breakdown voltages.
Innovation Solution
The implementation of an input stage with a separator transistor and a control circuit that limits reverse bias voltage across PN junctions, using a minimum voltage level selector and level shift circuit to isolate and separate the voltage across transistors, thereby preventing excessive reverse bias and reducing parasitic capacitance charging currents, while allowing high differential input voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If protection diodes are used to limit differential input voltage, then the input stage is protected against over-voltage, but large input current flows through the protection diodes when the input differential voltage exceeds the diode forward voltage
Solution Approach 1:
The patent introduces an intermediary protection circuit that includes series diodes and shunt transistors arranged to limit the voltage across the base-emitter junctions of the input transistors. This intermediary circuit prevents direct current flow through protection elements while still providing voltage limiting, thereby protecting the input stage without causing large input currents.
2Reliability
If a clamp circuit is used to protect against large differential voltage, then the reverse bias voltage across transistor junctions is limited, but the parasitic capacitance of input transistors is charged, degrading the output slew rate
Solution Approach 1:
The patent employs an intermediary protection network using series diodes and shunt transistors that limits voltage without directly charging the parasitic capacitances of the input transistors. The series diodes prevent excessive voltage development while the shunt transistors provide additional protection, collectively avoiding the slew rate degradation caused by parasitic capacitance charging.
Solution Approach 2:
The protection function is segmented into multiple independent elements: series diodes for voltage limiting and shunt transistors for additional protection. This segmentation allows each element to perform its specific function without the side effects of a single comprehensive clamp circuit, particularly avoiding the charging of parasitic capacitances that would degrade slew rate.
3Strength
If large input transistors are used to handle full supply voltage differential inputs, then the input stage can withstand higher voltages, but the parasitic capacitances increase, worsening the transient response
Solution Approach 1:
The patent introduces intermediary protection elements (series diodes and shunt transistors) that enable the use of larger input transistors with higher voltage withstand capability without suffering from increased parasitic capacitance penalties. The intermediary circuit limits the voltage stress on the transistors, allowing them to be sized for voltage handling rather than being constrained by transient response requirements.
Data Source
AI summary
Circuitry for preventing damage to bipolar transistors in integrated circuit amplifier circuitry during slew-limited operation includes first and second transistors, each having first, second, and third electrodes, a first one of the first and second electrodes of the first transistor being coupled to receive a first signal, and a first one of the first and second electrodes of the second transistor being coupled to receive a second signal. A first separator transistor having a first current-carrying electrode coupled to the first one of the first and second electrodes of the first transistor and a second current-carrying electrode coupled to the first one of the first and second electrodes of the second transistor is controlled so as to electrically isolate the first one of the first and second electrodes of the first transistor from the first one of the first and second electrodes of the second transistor in response to the first and second signals to limit a reverse bias voltage across a PN junction of one of the first and second transistors.