Memory String Erasure with Different Selection-Transistor Float Times
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Solution Overview
Problem
Inconsistent erase depths of memory strings due to process variation lead to lateral spreading and threshold voltage drift, affecting data retention in memory cells.
Innovation Solution
A method of operating memory by applying specific voltage sequences to selection transistors to control erase operations, including floating selection transistors at different times to manage erase depth and prevent over-erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If uniform erase operation is applied to all strings, then erase speed is improved, but erase depth consistency deteriorates due to process variation
Solution Approach 1:
The patent applies different float times to different strings based on their individual erase depth characteristics. Strings with deeper erase depths receive shorter float times, while strings with shallower erase depths receive longer float times. This localized adjustment compensates for process variations and achieves consistent erase depth across all strings without sacrificing overall erase speed.
Solution Approach 2:
The patent dynamically changes the float time parameter for each string based on measured erase depth. By adjusting this temporal parameter, the system optimizes the balance between erase speed and erase depth consistency, resolving the contradiction between maintaining high productivity and achieving precise erase depth control.
2Manufacturing precision
If longer float time is applied to achieve uniform erase depth, then erase depth consistency is improved, but erase operation time increases
Solution Approach 1:
Instead of uniformly extending the float time for all strings, the patent applies extended float time only to specific strings that require additional time to achieve target erase depth. This localized time extension maintains erase depth consistency while minimizing the overall erase operation time penalty.
Solution Approach 2:
The patent performs preliminary measurement of erase depth for each string before applying the float time adjustment. This preliminary action allows the system to pre-determine which strings need extended float time, enabling optimized erase operation sequencing that minimizes total operation time while ensuring consistent final erase depth across all strings.
3Reliability
If erase operation continues until all strings are fully erased, then complete erasure is achieved, but over-erasure of some strings occurs
Solution Approach 1:
The patent monitors erase depth individually for each string and applies different float time durations accordingly. Strings approaching complete erasure receive reduced or zero float time, preventing over-erasure, while strings that are not yet fully erased receive appropriate float time to achieve complete erasure. This localized control eliminates the harmful over-erasure effect while ensuring reliable complete erasure for all strings.
Solution Approach 2:
The patent implements a feedback mechanism where erase depth is measured for each string, and this measurement feeds back to determine the appropriate float time for the next erase cycle. This closed-loop control ensures that erase operations stop precisely when complete erasure is achieved for each string, preventing over-erasure while maintaining high reliability.
Data Source
AI summary
A memory, a memory system and a method of operating the memory are disclosed, belonging to the field of storage technologies. When an erase operation is performed on various strings in the block of the memory, if there are a first string that has been erased and a second string that has not been erased among the strings, the selection line coupled to the first selection transistor of the first string is floated in advance before the selection line coupled to the first selection transistor of the second string is floated, to thereby reduce the erasing speed of the first string and prevent the first string from being over-erased during the erasing of the second string, which reduces the possibility of lateral spreading of memory cells in the subsequent first string after programming, and weakens the threshold voltage drift of the memory cells in the first string.