Different-Thickness Gate Oxide Structures for FET Power Control
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Solution Overview
Problem
The complexity of semiconductor manufacturing processes increases with the scaling down of semiconductor devices, such as MOSFETs, finFETs, and GAA FETs, necessitating more cost-effective and time-efficient methods to form FET gate structures with varying power consumption levels without increasing gate resistance.
Innovation Solution
The method involves forming FETs with different gate oxide structures on a single substrate by using two oxidation processes to create first and second interfacial oxide layers with varying thicknesses, controlled by capping layers with different oxygen diffusivities, and incorporating high-k gate dielectric layers to achieve varying power consumption levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional single oxidation process is used to form gate oxide structures, then manufacturing process is simpler, but cannot achieve FETs with varying power consumption levels and different oxide thicknesses
Solution Approach 1:
The oxidation process is segmented into two distinct stages: a first oxidation process that forms an initial interfacial oxide layer with uniform thickness, and a second oxidation process that selectively thickens the oxide layer in specific regions. This segmentation allows different FETs on the same substrate to have different oxide thicknesses and thus different power consumption levels, while keeping each individual oxidation step relatively simple and controllable.
Solution Approach 2:
The first oxidation process performs a preliminary action by forming a uniform base interfacial oxide layer before the second oxidation process. This preliminary layer serves as a foundation that ensures consistent initial conditions across all FETs, while the subsequent selective oxidation can then be precisely controlled to create the desired thickness variations without compromising the uniformity of the base layer.
2Adaptability or versatility
If multiple separate manufacturing processes are used to form FETs with different power consumption levels, then power consumption variation is achieved, but manufacturing time and cost increase
Solution Approach 1:
Multiple oxidation steps that would traditionally be performed in separate manufacturing processes are merged into a single integrated sequence on the same substrate. The first and second oxidation processes are combined in one continuous flow, with the second oxidation selectively applied to specific regions after the first oxidation completes. This merging achieves diverse power consumption levels across different FETs while maintaining high manufacturing efficiency and avoiding the need for multiple separate process runs.
Solution Approach 2:
The dual oxidation process system serves multiple functions simultaneously: it creates uniform base oxide layers, generates selective thickness variations, enables power consumption control, and maintains compatibility with existing semiconductor manufacturing workflows. This multi-functionality allows a single manufacturing approach to produce FETs with different power consumption levels without requiring separate dedicated processes for each device type.
3Use of energy by moving object
If oxide layer thickness is increased to reduce power consumption, then power consumption decreases, but gate resistance may increase
Solution Approach 1:
The oxide layer thickness is optimized with local quality by having different thicknesses in different regions of the gate structure. The interfacial oxide layer provides a thin uniform base that maintains good electrical contact and low resistance, while selective thickening in specific regions reduces power consumption where needed. This local differentiation allows the structure to simultaneously achieve low power consumption and acceptable gate resistance by placing the right thickness in the right location.
Solution Approach 2:
The gate oxide structure functions as a composite material system with two distinct oxide layers: a thin uniform interfacial oxide layer that ensures low resistance and good electrical properties, and a selectively thickened oxide region that provides power consumption control. This composite structure combines the advantages of both thin and thick oxide regions, achieving a balance between electrical performance and power efficiency that neither uniform thin nor uniform thick oxide could achieve alone.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs by 20-30% and time by 15-20% while maintaining low power consumption and smaller dimensions without increasing gate resistance.
Implementation Method 1
using two oxidation processes to create first and second interfacial oxide layers with varying thicknesses
Implementation Method 2
controlled by capping layers with different oxygen diffusivities
Data Source
AI summary
A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The method includes forming first and second nanostructured channel regions on first and second fin structures, forming first and second oxide layers with first and second thicknesses, forming a dielectric layer with first and second layer portions on the first and second oxide layers, forming first and second capping layers with first and second oxygen diffusivities on the first and second layer portions, growing the first and second oxide layers to have third and fourth thicknesses, and forming a gate metal fill layer over the dielectric layer. The first and second thicknesses are substantially equal to each other and the first and second oxide layers surround the first and second nanostructured channel regions. The second oxygen diffusivity is higher than the first oxygen diffusivity. The fourth thickness is greater than the third thickness.