Differential ADC Feedback Circuit for Common-Mode Rejection Calibration
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Solution Overview
Problem
Biopotential acquisition systems face challenges in dealing with differential DC offset and achieving high common-mode rejection, particularly in power-constrained applications like Body Area Networks, where existing solutions like high-pass filtering and high-resolution ADCs are inefficient due to high power consumption and slow startup times.
Innovation Solution
A circuit with an analog input stage, analog-digital-converter, and digital-analog-converter in a feedback path for automatic common-mode rejection calibration, using sigma-delta converters to adapt and compensate for DC offsets, and modulating impedances to balance the circuit, thereby enhancing common-mode rejection and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-pass filtering is used to eliminate DC offset, then the DC component is removed, but the power consumption increases and startup time becomes slow
Solution Approach 1:
The patent extracts the DC offset component separately from the useful signal using a dedicated DC cancellation path. The DC offset is detected through a DC cancellation amplifier and removed through a summing amplifier, allowing the useful AC signal to be processed with much lower power consumption in subsequent stages.
Solution Approach 2:
The signal processing is segmented into two separate paths: one for DC offset cancellation and another for useful signal amplification. This segmentation allows each path to be optimized independently, with the DC path handling only the offset component and the main path handling the biopotential signal with minimal power consumption.
2Measurement precision
If high-pass filtering is used to eliminate DC offset, then the DC component is removed, but the startup time becomes slow
Solution Approach 1:
The DC offset is cancelled in advance through a dedicated cancellation path before the signal enters the main amplification stages. By performing DC cancellation preliminarily and continuously, the system achieves fast startup without waiting for filter settling times, as the DC path operates independently and immediately.
3Measurement precision
If high-resolution ADC is used to handle DC offset, then the DC component is processed, but the power consumption increases
Solution Approach 1:
The DC offset is extracted and handled separately through an analog cancellation path before digitization. Only the useful AC signal undergoes high-resolution ADC conversion, while the DC component is removed in the analog domain, significantly reducing the power consumption of the ADC and subsequent digital processing.
4Reliability
If symmetrical circuit is used to reduce common-mode effect, then the common-mode rejection is improved, but the operation point becomes unbalanced due to DC difference
Solution Approach 1:
The patent intentionally introduces asymmetry through a dedicated DC cancellation path that compensates for the DC difference between the two input channels. This asymmetric correction restores balance to the operation points of the symmetrical differential circuit, allowing it to maintain high common-mode rejection ratio without suffering from DC-induced unbalance.
Data Source
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AI summary
The present invention relates to a circuit and a method for automatic common- mode rejection calibration in a differential conversion system and unbalance compensation for balancing the operation point of a circuit in the signal path and for enhancing the common-mode rejection. The circuit for automatic common-mode rejection calibration in a differential conversion system comprises an analog input stage for an analog input signal (101), an analog-digital-converter (106) for converting an analog signal (107) into its digital representation (108), a digital block (105) arranged to adapt said digital representation (108) of a portion of a DC offset of said analog input signal (101) in accordance with whether said analog input signal (101) is in a predetermined input range of said analog-digital-converter (106), and a digital-analog-converter (103) arranged in a feedback path (102) from said digital block (105) to subtraction means (111) of said analog input stage for converting a digital signal (104) into an analog output signal (109), wherein said analog output signal (109) is subtracted from said analog input signal (101) resulting in said analog signal (107).