Differential ADC Ramp Control for Low-Harmonic Conversion

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Solution Overview

Problem

Existing differential hybrid analog-to-digital converters face control method disadvantages that affect their performance and efficiency.

Innovation Solution

A method for controlling an analog-to-digital converter that involves sampling a voltage using two digital-to-analog converters, determining most significant bits through successive approximations, and least significant bits through time-to-digital conversion with alternating voltage ramps, ensuring opposite variation directions based on the residual voltage sign.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If differential hybrid analog-to-digital converters are used to improve conversion speed and reduce power consumption, then conversion efficiency is improved, but harmonics generation and manufacturing dispersions increase

Engineering Contradiction:
Improveconversion speedVSAvoidharmonics generation
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent applies asymmetry by introducing opposite variation directions for the two ramps in the time-to-digital conversion stage. When the residual voltage is positive, the first ramp increases while the second ramp decreases, and vice versa. This asymmetric control of the ramps compensates for harmonics generation and manufacturing dispersions, resolving the contradiction between improved conversion efficiency and increased harmonics.

Inventive Principle:
Principle #4Asymmetry

2Productivity

If differential hybrid analog-to-digital converters are used to improve conversion speed, then productivity is improved, but manufacturing precision deteriorates

Engineering Contradiction:
Improveconversion speedVSAvoidmanufacturing dispersions
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent uses asymmetry in the ramp variation directions to compensate for manufacturing dispersions. By making the ramps vary in opposite directions based on the residual voltage sign, the system creates a self-correcting mechanism that reduces the impact of manufacturing variations on conversion precision, thereby resolving the contradiction between speed and precision.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent implements feedback by using the residual voltage from the successive approximations stage to control the direction of ramp variations in the time-to-digital conversion stage. This feedback mechanism allows the system to adjust the ramp behavior based on the conversion remainder, improving manufacturing precision while maintaining high conversion speed.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If time-to-digital conversion is used to determine least significant bits, then conversion accuracy is improved, but harmonics of order two increase

Engineering Contradiction:
Improveconversion accuracyVSAvoidharmonics of order two
Core Design Contradiction:
Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The patent applies asymmetry by making the two ramps vary in opposite directions during time-to-digital conversion. This asymmetric behavior of the ramps compensates for the harmonics of order two that are inherently generated by the time-to-digital conversion process, allowing the system to maintain high conversion accuracy while reducing harmful harmonic effects.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS12463655B2Method for controlling an analog-to-digital converter
Publication Date: 2025.11.04 STMICROELECTRONICS (ALPS) SAS
  • US12463655B2 patent drawing
  • US12463655B2 patent drawing
  • US12463655B2 patent drawing

AI summary

The present description concerns a method of controlling an analog-to-digital converter, wherein most significant bits are determined by successive approximations implementing a first digital-to-analog converter and a second digital-to-analog converter. Further, least significant bits are determined by a time-to-digital conversion by applying a first ramp to the output of the first converter with a third digital-to-analog converter and by applying a second ramp to the output of the second converter with a fourth digital-to-analog converter. The variation direction of the first and second ramps is determined by the comparison of the outputs of the first and second converters at the end of the successive approximations.