Differential Subrange ADC With Shared Comparator for Noise Reduction
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Solution Overview
Problem
Current CMOS image sensors face challenges in reducing noise in image data, particularly due to fixed pattern and temporal noise, which affect image quality, and existing analog or digital correlated double sampling methods may not be optimal for all applications.
Innovation Solution
A differential subrange analog-to-digital converter (ADC) circuit with selectable buffered bit capacitors is introduced, which converts the difference between signal and reset voltages into digital output, utilizing a combination of successive approximation register (SAR) and ramp ADC techniques to enhance noise reduction and image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If correlated double sampling is implemented to reduce noise, then noise reduction is improved, but device complexity increases
Solution Approach 1:
The patent combines the CDS subtraction operation with the ADC conversion process into a single integrated circuit block. The differential subrange ADC directly processes the difference between signal and reset voltages, eliminating the need for separate CDS and ADC stages. This merging reduces device complexity while maintaining the noise reduction benefits of CDS.
Solution Approach 2:
The integrated circuit performs multiple functions simultaneously: it executes correlated double sampling to reduce noise, performs analog-to-digital conversion, and handles differential voltage processing all within a single device. This multi-functionality reduces the overall system complexity while achieving noise reduction.
2Measurement precision
If the number of pixels is increased to improve image quality, then image quality is improved, but device complexity increases
Solution Approach 1:
The patent changes the operational parameters of the ADC by implementing a differential subrange architecture that processes voltage differences rather than absolute values. This parameter change enables the system to handle higher pixel densities more efficiently, as the differential processing reduces the dynamic range requirements and simplifies the conversion process for each pixel.
3Measurement precision
If successive approximation register and ramp ADC techniques are combined, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the ADC conversion process into two distinct phases: a successive approximation register (SAR) phase for coarse conversion and a ramp ADC phase for fine conversion. This segmentation allows each sub-process to be optimized independently and then combined to achieve high overall precision. The segmented approach reduces complexity compared to implementing a single high-precision ADC architecture.
Solution Approach 2:
The patent adds a temporal dimension to the conversion process by sequentially executing SAR and ramp conversion stages rather than attempting single-stage conversion. This dimensional approach to conversion allows the system to achieve high precision through multi-stage processing, reducing the complexity requirements of any single conversion stage.
Data Source
AI summary
A differential subrange analog-to-digital converter (ADC) converts differential analog image signals received from sample and hold circuits to a digital signal through an ADC comparator. The comparator of the differential subrange ADC is shared by a successive approximation register (SAR) ADC coupled to provide both M upper output bits (UOB) and a ramp ADC coupled to provide N lower output bits (LOB). Digital-to-analog converters (DACs) of the differential subrange SAR ADC comprises 2M buffered bit capacitor fingers connected to the comparator. Each buffered bit capacitor finger comprises a bit capacitor, a bit buffer, and a bit switch controlled by the UOB. Both DACs are initialized to preset values and finalized based on the values of the least significant bit of the UOB. The subsequent ramp ADC operation will be ensured to have its first ramp signal ramps in a monotonic direction and its second ramp signal ramp in an opposite direction.