Differential ADC Timing Conversion Without Modulo Processing
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Solution Overview
Problem
Current analog to digital converters lack the necessary accuracy and efficiency in converting analog signals to digital signals, particularly in determining the difference between differential input signals.
Innovation Solution
The proposed ADC system includes a signal generator that produces phase-shifted clock signals and PWM-related signals, which are processed to generate virtual counter and phase values, allowing for the determination of the signal difference through linear operations without modulo operations, thereby simplifying the process and reducing resource consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional analog to digital conversion methods are used, then the conversion process is simpler, but the accuracy and precision in determining signal differences deteriorates
Solution Approach 1:
The patent segments the analog signal processing into distinct phases using phase-shifted clock signals. The counter output is sampled at multiple phase points (0°, 90°, 180°, 270°), dividing the conversion process into manageable segments that can be processed independently and combined to achieve high precision without overwhelming complexity.
Solution Approach 2:
The patent introduces virtual counter values and virtual phase values as intermediary elements. These virtual values serve as mediators that align the sampled data from different phases, enabling accurate difference determination through linear operations while avoiding the complexity of direct modulo operations on raw sampled data.
2Productivity
If modulo operations are used to determine signal differences, then the conversion can be performed, but the resource consumption and processing time increases
Solution Approach 1:
The patent replaces the mechanical/mathematical modulo operation with an equivalent linear operation using virtual counter values. Instead of performing computationally intensive modulo operations on sampled counter values, the system uses virtual counter values that are aligned through phase relationships, allowing difference determination through simple subtraction and linear combination, significantly reducing processing resources and energy consumption.
3Measurement precision
If phase-aligned virtual counter values are generated, then the accuracy of difference determination improves, but the processing complexity increases
Solution Approach 1:
The patent employs periodic phase-shifted clock signals to sample the counter output at regular phase intervals (0°, 90°, 180°, 270°). This periodic sampling creates a predictable pattern of virtual counter values and phase values that are inherently aligned, reducing the complexity of the alignment process while maintaining high precision in difference determination.
Data Source
AI summary
An analog to digital converter (ADC) receives first and second analog input signals. A charge sampling demultiplexer includes multiple capacitors that sample the first and second analog input signals, and generates multiple input samples representative of charge stored on the capacitors. A plurality of sub-ADCs each include first and second charge-to-time converters, which receive from the charge sampling demultiplexer respective first and second input sample of the first and second analog input signals and output respective first and second pulse-width-modulated (PWM) signals responsively to the respective first and second input samples. Temporal processing circuitry processes the PWM signals to generate a digital value indicative of a temporal difference between the first and second PWM signals. Output reordering circuitry receives the digital value from each of the sub-ADCs and generates a digital output indicative of a difference between the first and second analog input signals.