Differential Amplifier Common-Mode Compensation for Low-Voltage Stability
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Solution Overview
Problem
Low-voltage operational transconductance amplifiers (OTAs) face instability due to poor common-mode-rejection-ratio (CMRR) and undesired common-mode current injection, particularly at low supply voltages, leading to instability in the common-mode feedback loop.
Innovation Solution
A resistor-capacitor (RC) network is introduced to duplicate the biasing network of the tail current source, adding a compensation path with a capacitor and resistor to propagate common-mode perturbations to the gate of a transistor, mirroring a compensation current into the tail current source for AC and DC cancellation of common-mode current, thereby improving stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a resistance is connected in series to the Miller capacitance to increase phase margin, then the phase margin is improved, but the differential feedback of the amplifier is adversely impacted
Solution Approach 1:
The patent segments the feedback mechanism into two independent paths: a differential feedback path and a common-mode feedback path. The differential feedback path maintains stability through the Miller capacitance, while the common-mode feedback path uses a separate transistor (third transistor) and resistor network to handle common-mode signals. This segmentation allows each path to be optimized independently without interfering with the other.
Solution Approach 2:
The patent introduces a third transistor as an intermediary element that couples the output nodes to the tail node through a resistor network. This intermediary transistor acts as a mediator that specifically targets common-mode signals while leaving differential signals unaffected. The resistor network connected to the gate of this third transistor serves as an intermediary filtering mechanism that separates common-mode from differential components.
2Use of energy by moving object
If the area of the input differential pair is increased to push input MOSFET transistors into subthreshold condition, then efficiency is improved, but area expansion occurs particularly at low supply voltages
Solution Approach 1:
The patent changes the operating parameters of the transistors by introducing the third transistor and resistor network to create specific voltage conditions. The resistor network connected to the gate of the third transistor adjusts the gate-source voltage to push the input MOSFET transistors into subthreshold operation, achieving high efficiency without requiring increased transistor area. This parameter change approach allows efficiency optimization through voltage control rather than area scaling.
3Use of energy by moving object
If low-voltage transistors are used in operational amplifiers, then power consumption is reduced, but common-mode-rejection-ratio deteriorates leading to instability
Solution Approach 1:
The patent implements a dedicated common-mode feedback mechanism using the third transistor and resistor network. The resistor network monitors the common-mode voltage at the tail node and feeds back control signals through the third transistor to the output nodes. This feedback loop actively compensates for common-mode disturbances, maintaining high CMRR even when using low-voltage transistors that would otherwise exhibit poor common-mode rejection.
Data Source
AI summary
A differential input stage includes first and second input transistors with current flow paths are coupled between a tail transistor current flow path and first and second nodes, respectively. An output stage includes first and second output transistors having current flow paths between a supply line and first and second output nodes, respectively, coupled to the first and second nodes. First and second common-mode control transistors have current flow paths jointly coupled to a ground current flow path of a common-mode tail transistor. The first common-mode control transistor has a control terminal resistively coupled to the first and second output nodes. A bias duplicate transistor has a current flow path arranged in a bias current flow line between the supply line and ground. The bias duplicate transistor is coupled in a 1:N current mirror arrangement with the tail transistor in the differential input stage.