Differential Amplifier Circuit for Common-Mode Shift With Low Capacitance
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Solution Overview
Problem
High-speed serial transmission circuits face challenges with increased input capacitance and power consumption due to the need for multiple level shift circuits to manage common-mode voltage levels, which narrows bandwidth and raises power consumption.
Innovation Solution
A differential amplifier circuit design that includes cascode-connected transistors with specific impedance elements and capacitors to manage common-mode voltage levels, reducing input capacitance and power consumption while maintaining high bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two or more level shift circuits are provided in the preamplifier to output differential signals with different common-mode voltages, then the common-mode voltage levels can be managed appropriately, but the input capacitance increases and the bandwidth decreases
Solution Approach 1:
The patent combines multiple level shift functions into a single level shift circuit by using a differential amplifier that directly outputs differential signals with different common-mode voltages. This merging eliminates the need for separate level shift circuits for each differential signal pair, thereby reducing input capacitance and maintaining bandwidth while still achieving appropriate common-mode voltage management.
Solution Approach 2:
The differential amplifier is designed to perform multiple functions simultaneously: it amplifies the differential signal and also generates different common-mode voltage levels for different output pairs. This multi-functionality eliminates the need for dedicated level shift circuits, reducing the overall circuit complexity and input capacitance while maintaining the required voltage level management.
2Reliability
If two or more level shift circuits are provided in the preamplifier to output differential signals with different common-mode voltages, then the common-mode voltage levels can be managed appropriately, but the power consumption increases
Solution Approach 1:
The patent combines multiple level shift functions into a single level shift circuit by using a differential amplifier that directly outputs differential signals with different common-mode voltages. This merging eliminates the need for separate level shift circuits for each differential signal pair, thereby reducing input capacitance and maintaining bandwidth while still achieving appropriate common-mode voltage management.
Solution Approach 2:
The differential amplifier is designed to perform multiple functions simultaneously: it amplifies the differential signal and also generates different common-mode voltage levels for different output pairs. This multi-functionality eliminates the need for dedicated level shift circuits, reducing the overall circuit complexity and input capacitance while maintaining the required voltage level management.
3Speed
If cascode-connected transistors with specific impedance elements and capacitors are used to manage common-mode voltage levels, then input capacitance is reduced and bandwidth is broadened, but the device complexity increases
Solution Approach 1:
The patent uses cascode-connected transistors with specifically designed impedance elements and capacitors to control the common-mode voltage levels. By carefully selecting and adjusting these circuit parameters, the design achieves reduced input capacitance and broadened bandwidth while managing the complexity through systematic parameter optimization rather than overly complex circuit topologies.
Data Source
AI summary
A differential amplifier circuit has a first current circuit comprising a first transistor and a second transistor, and to flow a current depending on a voltage of a first input signal, a second current circuit comprising a third transistor and a fourth transistor, and to flow a current depending on a voltage of a second input signal, a fifth transistor comprising a gate connected to a gate and the drain of the second transistor, and to flow a current that is M times greater than the current flowing between the drain and the source of the second transistor, and a sixth transistor comprising a gate connected to a gate and the drain of the fourth transistor and cascode-connected to the first transistor, and to flow a current that is N times greater than the current flowing between the drain and the source of the fourth transistor.


