Differential Amplifier Using Odd-Phase Averaging for Duty Cycle Accuracy
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Solution Overview
Problem
Conventional CMOS differential amplifiers in phase locked loops (PLL) and delay locked loops (DLL) experience duty cycle distortion when processing odd-numbered phase signals, leading to increased power consumption and load on the voltage-controlled oscillator due to the need for phase interpolation to achieve a 180-degree phase difference.
Innovation Solution
A differential amplifier design that includes an input stage receiving a first phase signal and at least two odd-numbered phase signals with an average phase difference of 180 degrees, coupled with a biasing unit and a load unit to output a differential signal, effectively reducing duty cycle distortion by selecting phase signals such that the average phase difference between the second and third phase signals is 180 degrees from the first phase signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If phase interpolation circuit is used to provide differential signals with 180-degree phase difference from odd-numbered phase signals, then duty cycle distortion is reduced, but power consumption increases and load on VCO increases
Solution Approach 1:
The patent extracts and eliminates the phase interpolation circuit from the system by directly selecting appropriate odd-numbered phase signals (e.g., signals at 72° and 216°) that inherently provide the required 180-degree phase difference when combined with a reference signal. This removal of the interpolation circuit directly reduces power consumption while maintaining duty cycle accuracy.
Solution Approach 2:
The patent makes the VCO's phase signals serve multiple functions: they simultaneously provide the clock signals for the differential amplifier and inherently contain the 180-degree phase relationship needed for duty cycle correction, eliminating the need for separate phase interpolation functionality.
2Manufacturing precision
If phase interpolation circuit is used to provide differential signals with 180-degree phase difference, then duty cycle distortion is reduced, but load on VCO increases
Solution Approach 1:
The patent removes the phase interpolation circuit that added complexity and load to the VCO. Instead, it directly utilizes the VCO's existing odd-numbered phase signals, thereby reducing the overall system complexity and the load burden on the VCO while achieving the same duty cycle correction objective.
Solution Approach 2:
The patent merges the function of phase interpolation into the direct signal selection process by choosing odd-numbered phase signals that naturally provide the 180-degree phase relationship, combining the VCO output and phase difference generation into a single integrated approach that reduces complexity.
3Device complexity
If conventional CMOS differential amplifier processes odd-numbered phase signals, then circuit simplicity is maintained, but duty cycle distortion occurs in the output signal
Solution Approach 1:
The patent changes the phase parameter selection by specifically choosing odd-numbered phase signals with predetermined phase relationships (e.g., 72° and 216° signals that provide 180° difference) as inputs to the conventional CMOS differential amplifier. This parameter change enables the simple circuit to produce accurate 50% duty cycle outputs without modification to the amplifier itself.
Data Source
AI summary
A differential amplifier includes an input stage, a biasing unit and a load unit. The input stage receives a first phase signal and at least two phase signals among odd-numbered phase signals, wherein an average of phases of the at least two phase signals has a phase difference of substantially 180 degrees from the first phase signal. The biasing unit is coupled between the input stage and a first power voltage. The load unit is coupled between the input stage and a second power voltage, and configured to output a differential output signal based on differentially amplifying of the first phase signal and the at least two phase signals. Therefore, a duty cycle distortion in an output signal of a duty cycle correction circuit can be prevented.