Differential Amplifier Load Circuit for High-Speed Signal Amplitude

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Solution Overview

Problem

In semiconductor devices with differential amplifier circuits, achieving high-speed operation while maintaining appropriate signal amplitudes and reducing inter-symbol interference (ISI) is challenging due to the limitations of diode-connected transistors, which can lead to decreased gain and accuracy.

Innovation Solution

The combination of cross-coupled and assist circuits in the differential amplifier circuit, with the removal of diode-connected transistors, optimizes signal amplitudes and enhances the gain, allowing for faster operation by adjusting current mirror ratios and potential adjustments through intermediate nodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If diode-connected transistors are used in the differential amplifier circuit, then the circuit structure is simplified, but the gain and signal amplitude are reduced

Engineering Contradiction:
Improvecircuit structureVSAvoidgain and signal amplitude
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The load circuit is segmented into multiple transistors (first through fourth transistors) with distinct functions: cross-coupled transistors for speed enhancement and non-cross-coupled transistors for gain maintenance. This segmentation allows the circuit to achieve both high speed and high gain without relying on diode-connected transistors that would compromise signal amplitude.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent merges two functional approaches: cross-coupled transistor configuration for speed improvement and non-cross-coupled transistor configuration for gain maintenance. By combining these configurations in a single load circuit, the differential amplifier achieves both high-speed operation and high signal amplitude simultaneously.

Inventive Principle:
Principle #5Merging (Combining)

2Speed

If cross-coupled transistor configuration is used to speed up operation, then the operating speed is improved, but the signal amplitude decreases

Engineering Contradiction:
Improveoperating speedVSAvoidsignal amplitude
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

Different regions of the load circuit have different configurations optimized for different functions: cross-coupled transistors (first and second) are positioned to provide speed enhancement, while non-cross-coupled transistors (third and fourth) are positioned to maintain gain and signal amplitude. This local quality differentiation resolves the contradiction between speed and signal amplitude.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If diode-connected transistors are used, then the circuit is easier to manufacture, but manufacturing variations have greater impact on performance

Engineering Contradiction:
Improvemanufacturing processVSAvoidperformance stability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent uses current mirror circuits (fifth and sixth transistors) to copy and replicate current characteristics throughout the circuit. This copying mechanism ensures that manufacturing variations in one transistor are compensated by corresponding adjustments in mirrored transistors, reducing the overall impact of manufacturing variations on circuit performance.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS10819295B2Semiconductor device and memory system
Publication Date: 2020.10.27 KIOXIA CORP
  • US10819295B2 patent drawing
  • US10819295B2 patent drawing
  • US10819295B2 patent drawing

AI summary

According to one embodiment, there is provided a semiconductor device comprising a first differential amplifier circuit. The first differential amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The second transistor's gate and drain are connected to the first transistor. The third transistor is diode-connected through the first transistor or diode-connected without passing through the first transistor. The fourth transistor is diode-connected through the second transistor or diode-connected without passing through the second transistor. The fifth transistor forms a first current mirror circuit with the third transistor. The sixth transistor is connected to a drain of the first transistor in parallel with the third transistor and forms a second current mirror circuit with the fifth transistor.