Differential Amplifier Load Segmentation for Low-Voltage A/D Converters
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Solution Overview
Problem
Differential amplifier circuits in high-speed A/D converters face performance degradation when operating at low power supply voltages, leading to reduced speed performance and overdrive recovery issues due to the diode-connected transistor load's clamp effect, which limits the output common voltage and biases the NMOS transistors out of the saturated region.
Innovation Solution
The implementation of parallel amplification degree adjustment units with load transistors that control the output common voltage, allowing the differential amplifier circuit to operate with high gain during small amplitude signals and exhibit a clamp effect during large amplitude signals, maintaining high-speed operation even at low power supply voltages by adjusting the amplification units' state based on input conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a diode connected transistor load is used in a differential amplifier, then the clamp effect prevents output spreading and increases overdrive recovery speed, but the output common voltage is limited and NMOS transistors are biased out of the saturated region at low power supply voltages
Solution Approach 1:
The load transistor is divided into two separate functional components: a first load transistor configured to clamp the output common voltage to maintain NMOS transistors in the saturated region, and a second load transistor providing the clamp effect for overdrive recovery. This segmentation allows each component to independently fulfill its specific function without interfering with the other, resolving the contradiction between maintaining saturation operation and achieving fast overdrive recovery.
Solution Approach 2:
Different parts of the load circuit are given different electrical characteristics: the first load transistor is optimized for voltage clamping to ensure saturation, while the second load transistor is optimized for rapid response to provide overdrive recovery. This local differentiation of functional qualities allows the circuit to simultaneously achieve both goals that were previously mutually exclusive.
2Use of energy by stationary object
If the power supply voltage is reduced, then power consumption is decreased, but the output common voltage becomes insufficient and performance degrades
Solution Approach 1:
The first load transistor proactively clamps the output common voltage to a level that ensures NMOS transistors remain in the saturated region, counteracting the tendency for voltage droop that occurs at low power supply voltages. This preliminary protective action prevents performance degradation before it can occur, allowing the circuit to maintain reliable operation even when the power supply voltage is reduced.
3Measurement precision
If the amplification degree is increased for small amplitude signals, then gain is improved, but excessive amplification occurs during large amplitude signals causing output spreading
Solution Approach 1:
The second load transistor dynamically adjusts its conduction state based on the input signal amplitude: for small amplitude signals, it remains inactive allowing high gain amplification; for large amplitude signals, it activates to provide clamping and prevent excessive output spreading. This dynamic adaptation of circuit characteristics resolves the contradiction between achieving high gain and preventing output saturation.
Data Source
AI summary
PMOS transistors are interposed parallel to each other between a node, which is a first output part, and a power supply; and PMOS transistors are interposed in parallel to each other between a node, which is a second output part, and the power supply. Output voltages in time of a balanced state in which an input potential difference between an input voltage and a reference voltage is “0” are both set to a reference output common voltage by a replica circuit and a comparator. The reference output common voltage of the replica circuit is set so that the potential difference between the power supply voltage and the output common voltage becomes a value lower than a threshold voltage of the diode connected PMOS transistors.