Differential Amplifier Topology for Low-Noise MEMS Sensor Biasing
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Solution Overview
Problem
Existing differential amplifiers for capacitive MEMS sensors face challenges in reducing power consumption and semiconductor area while maintaining low noise and reliability, particularly due to the need for high-ohmic resistances that are either costly or noisy when implemented as passive or active components.
Innovation Solution
A differential amplifier with quasi-infinite common-mode sensor resistance based on transistors connected in antiparallel via diodes, eliminating the need for high-ohmic passive and active resistances, which reduces noise propensity and preserves the differential gain stage, allowing for rail-to-rail operation and efficient signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-ohmic resistances are implemented as passive components, then the common-mode sensor resistance can be achieved, but the semiconductor area becomes excessively large
Solution Approach 1:
The patent replaces passive resistive components with active transistor-based circuits to generate high-ohmic common-mode sensor resistance. The first and second transistors are configured in a specific arrangement where their combined resistance in the common-mode path achieves several megaohms without requiring large physical resistor structures, thus reducing semiconductor area while maintaining the required resistance level.
Solution Approach 2:
The patent changes the approach from using fixed passive resistance values to dynamically controlling resistance through transistor operation. By adjusting transistor biasing and operating points, the common-mode sensor resistance can be optimized to achieve high resistance values with compact transistor structures instead of large passive components.
2Area of stationary object
If active structures with transistors and resistive T-network are used to save space, then the semiconductor area is reduced, but the noise level increases significantly
Solution Approach 1:
The patent applies different circuit configurations to different parts of the amplifier. The first transistor handles differential signals with low noise requirements, while the second transistor is specifically configured for common-mode feedback where high resistance is needed. This localized optimization allows space reduction without compromising overall noise performance.
Solution Approach 2:
The patent introduces a carefully designed transistor network as an intermediary between the input stage and the output, which provides the necessary high common-mode impedance without directly coupling noisy active structures to sensitive signal paths. The configuration acts as a buffer that isolates noise sources while maintaining signal integrity.
3Object-affected harmful factors
If fully differential amplifiers with continuous time base are used, then common-mode noises can be suppressed, but power consumption increases
Solution Approach 1:
The patent employs periodic switching of transistors in the feedback network to achieve continuous-time common-mode feedback with reduced power consumption. By alternately activating different transistor pairs synchronized with the signal period, the circuit maintains effective common-mode rejection while allowing individual transistors to rest, thereby reducing average power consumption compared to continuously active differential pairs.
Data Source
AI summary
A differential amplifier for operating a sensor. The differential amplifier includes a first two-pole and a second two-pole. A first terminal of the first two-pole is connected to a drain terminal of a current source of a master amplifier of the differential amplifier, and a second terminal of the first two-pole is connected to a first terminal of the second two-pole. A second terminal of the second two-pole is furthermore connected to a source terminal of an input transistor of the master amplifier. The first two-pole includes a first and a second semiconductor switch, which are connected in antiparallel to one another, and the second two-pole includes a third and a fourth semiconductor switch, which are connected in antiparallel to one another.

