Differential Amplifier Circuit With Capacitor Mismatch Cancellation
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Solution Overview
Problem
Existing differential amplifier circuits require complex switching networks and separate 'sample & hold' stages, leading to increased power consumption and die space, which is not cost-effective for integrated circuits used in devices that require improved battery performance.
Innovation Solution
A differential amplifier circuit with capacitor mismatch error cancellation using a simplified switching network and a single amplifier stage, comprising a pair of capacitors and a switching network that operates in multiple configurations to achieve unity gain and cancel capacitor mismatch errors, reducing power consumption and die space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a complex switching network and separate sample & hold stages are used to achieve capacitor mismatch error cancellation, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent combines the sample & hold functionality directly within the differential amplifier stage by using the capacitor pair as both the feedback element and the sampling mechanism. This integration eliminates the need for separate sample & hold stages and simplifies the switching network topology while maintaining capacitor mismatch error cancellation capability.
Solution Approach 2:
The capacitor pair in the differential amplifier serves multiple functions simultaneously: it provides feedback for gain control, performs sampling of the input signal, and enables capacitor mismatch error cancellation through the correlated double sampling technique. This multi-functionality reduces the overall component count and circuit complexity.
2Measurement precision
If a complex switching network and separate sample & hold stages are used, then measurement precision is improved, but power consumption increases
Solution Approach 1:
By integrating the sample & hold functionality into the differential amplifier stage, the patent reduces the number of active components and switching operations required. This integration directly reduces dynamic power consumption associated with charging and discharging capacitors in separate stages, while maintaining the precision benefits of capacitor mismatch error cancellation.
3Measurement precision
If a complex switching network and separate sample & hold stages are used, then measurement precision is improved, but area occupied increases
Solution Approach 1:
The patent integrates the sample & hold circuitry within the differential amplifier stage, eliminating the need for separate sample & hold stages. This integration significantly reduces the die area required by removing redundant capacitors and switching networks, while preserving the capacitor mismatch error cancellation functionality through the unified capacitor pair architecture.
Data Source
AI summary
A differential amplifier circuit comprising a differential amplifier capacitor and a mismatch error cancellation circuitry, a first pair of capacitors, a second pair of capacitors consisting of switching network. The switching network is arranged to operate in a first configuration wherein the first pair of capacitors is operably coupled to differential inputs of the differential amplifier circuit. The switching network is further arranged to operate in second configuration wherein each capacitor of the first pair of capacitors is operably coupled within a feedback loop between an output and an input of the differential amplifier such that the differential amplifier outputs signals representative of the sampled input voltage signals, and the second pair of capacitors are operably coupled in parallel between the outputs of the differential amplifier such that the second pair of capacitors sample the voltage difference between the outputs.