Differential Amplifier Noise Cancellation for Wideband Low-Power RF

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Solution Overview

Problem

Future wireless communication networks, particularly fifth-generation networks, require receivers that operate at high frequencies with low noise and low power consumption, necessitating an improved amplifier design to achieve large communication bandwidth and efficient noise suppression.

Innovation Solution

The amplifier design incorporates a differential pair configuration with transistors arranged in common-gate and common-source configurations, along with inductive and load elements, to achieve noise cancellation independent of output impedance, enabling wide bandwidth and low power consumption. The transconductance ratios of the transistors are carefully managed to optimize noise cancellation and bandwidth trade-offs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional LNA design is used, then noise performance may be acceptable, but bandwidth is limited and power consumption increases

Engineering Contradiction:
Improvenoise performanceVSAvoidbandwidth
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The amplifier is divided into multiple functional blocks: a first amplifier stage with common-gate and common-source transistors for noise cancellation, a second amplifier stage for signal amplification, and separate inductive matching networks. This segmentation allows each stage to be optimized independently, enabling wide bandwidth while maintaining low noise performance through the noise-cancelling first stage.

Inventive Principle:
Principle #1Segmentation

2Object-affected harmful factors

If noise cancellation techniques are implemented, then noise suppression improves, but device complexity increases

Engineering Contradiction:
Improvenoise suppressionVSAvoidamplifier structure
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent combines common-gate and common-source transistor configurations within the same amplifier stage to achieve noise cancellation. The common-gate transistors provide input buffering and noise cancellation, while the common-source transistors provide voltage gain. This merging of configurations in a unified differential amplifier structure achieves effective noise suppression without requiring separate complex noise-cancellation circuits.

Inventive Principle:
Principle #5Merging (Combining)

3Speed

If high frequency operation is implemented, then communication capacity increases, but power consumption increases

Engineering Contradiction:
Improveoperating frequencyVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent employs inductive matching networks with adjustable inductance values to optimize the amplifier's input and output impedance matching at high frequencies. By carefully selecting and tuning the inductance parameters of the matching networks, the amplifier achieves maximum power transfer and minimum reflected power at the operating frequency, thereby improving power efficiency and reducing overall power consumption during high-frequency operation.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10326410B2Amplifier adapted for noise suppression
Publication Date: 2019.06.18 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US10326410B2 patent drawing
  • US10326410B2 patent drawing
  • US10326410B2 patent drawing

AI summary

Systems and methods of noise suppression by an amplifier are presented. In one exemplary embodiment, an amplifier comprises first and fourth transistors configured as a first differential pair of transistors in a common-gate configuration, and second and third transistors configured as a second differential pair of transistors in a common-source configuration. The first and fourth transistors are operative to receive, from a differential input, by a source of each first and fourth transistor, a differential input signal. Further, a drain of each first and fourth transistor is coupled to respective first and second outputs configured as a differential output. The second and third transistors are operative to output, from a drain of each second and third transistor, to the respective second and first outputs, a differential output signal. Further, a gate of each second and third transistor is coupled to the respective first and second inputs.