Differential Input Amplifier Switching Without Shared Pair Current
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Solution Overview
Problem
The existing differential input circuits face instability in amplification ratio and operation stability when the in-phase input voltage equals the reference voltage, leading to shared current between PMOS and NMOS differential input pairs, which limits high-speed switching due to increased parasitic capacitance as the PMOS transistor size increases.
Innovation Solution
Incorporating comparators and a NAND gate to control the gate voltage of the PMOS transistor, allowing for a logic signal to manage the operation of the PMOS transistor, thereby preventing shared current and reducing parasitic capacitance, ensuring stable operation even at equal input voltage conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PMOS transistor size is increased to prevent shared current, then operation stability is improved, but parasitic capacitance increases which limits high-speed switching
Solution Approach 1:
The comparators C1 and C2 perform preliminary detection of the input voltage levels relative to the reference voltage VREF before the differential input pairs operate. This preliminary action allows the system to proactively switch between PMOS and NMOS pairs based on predicted operating conditions, preventing the shared current problem before it occurs and enabling high-speed switching without requiring oversized transistors.
Solution Approach 2:
The NAND gate N1 acts as an intermediary between the comparators and the differential input pairs, translating the comparator outputs into appropriate control signals for the PMOS transistor Q5. This intermediary component coordinates the switching action, ensuring that the PMOS and NMOS differential input pairs do not operate simultaneously, thus preventing shared current while maintaining high-speed performance.
2Reliability
If comparators and logic circuits are added to control PMOS transistor, then shared current is prevented, but circuit area increases
Solution Approach 1:
The invention changes the operating parameters of the differential input circuit by introducing voltage threshold comparisons through comparators. Instead of using a single large PMOS transistor, the system uses parameter-based control (voltage level detection) to dynamically switch between PMOS and NMOS differential input pairs, achieving stable operation with smaller transistor sizes and reduced overall circuit area.
Data Source
AI summary
The present disclosure provides a differential input circuit. The differential input circuit includes: a P-channel FET differential input pair; an N-channel FET differential input pair; a first power line configured to receive a first voltage; a second power line configured to receive a second voltage lower than the first voltage; a first P-channel FET; a constant current source (CS1) disposed between the first power supply line and the P-channel FET differential input pair as well as the first P-channel FET; a current mirror circuit disposed between the first P-channel FET as well as the N-channel FET differential input pair and the second power supply line; and a logic circuit configured to supply a binarized logic signal to a gate of the first P-channel FET.