Differential Amplifier Tail Stub Layout for High CMRR at 300 GHz
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Solution Overview
Problem
Conventional differential amplifier circuits face challenges in achieving a large common mode rejection ratio (CMRR) while maintaining low power consumption, especially at frequencies above 300 GHz, due to increased power consumption and difficulties in realizing suitable inductors for integrated circuit processes.
Innovation Solution
A differential amplifier circuit design incorporating a short stub as a tail current circuit, with an electrical length shorter than a quarter wavelength, and additional components like capacitance and resistors to enhance CMRR, allowing for a symmetrical structure and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a current source transistor Q3 is used to operate in saturation region for high impedance, then common mode rejection ratio is improved, but power consumption increases due to bias voltage VGG1
Solution Approach 1:
The patent changes the operating parameters by using an inductor L1 instead of a current source transistor Q3 for the tail current circuit. This substitution modifies the impedance characteristics at the intersection point X, achieving high impedance for common mode signals without requiring the bias voltage VGG1, thereby reducing power consumption while maintaining common mode rejection ratio.
Solution Approach 2:
The patent replaces the active current source transistor Q3 with a passive inductor L1 in the tail current circuit. This substitution eliminates the need for bias voltage VGG1 and the associated power consumption, while the inductor provides the necessary high impedance for common mode signal rejection through its reactive impedance at the operating frequency.
2Use of energy by moving object
If inductor L1 is used as tail current circuit to reduce power consumption, then power supply voltage VDD is reduced, but it becomes difficult to realize suitable inductors for integrated circuit processes at frequencies above 300 GHz
Solution Approach 1:
The patent optimizes the inductor design by carefully selecting its inductance value and quality factor to achieve the desired high impedance at the operating frequency while minimizing the physical size. The inductor is designed to provide sufficient reactance for common mode rejection without requiring large physical dimensions that would be difficult to integrate at 300 GHz and above.
Solution Approach 2:
The patent applies local quality enhancement by using high-quality factor inductor designs and optimizing the layout to minimize parasitic effects. The inductor is strategically positioned and designed with specific geometric characteristics to maximize its effectiveness in the tail current circuit while maintaining compatibility with standard integrated circuit fabrication processes at high frequencies.
3Power
If transistors are made multi-stage to achieve sufficient gain at 300 GHz or more, then gain is improved, but power consumption inevitably increases
Solution Approach 1:
The patent changes the circuit topology by using a single-stage differential amplifier configuration with an optimized tail current circuit consisting of inductor L1. This topological change allows the circuit to achieve sufficient gain at 300 GHz and above without requiring multiple transistor stages, thereby avoiding the proportional increase in power consumption that would result from cascading multiple amplification stages.
Data Source
AI summary
An embodiment differential amplifier circuit includes an amplifier section including differential pair transistors to which a differential signal is input and a tail current circuit made up of a short stub provided between a ground terminal of the amplifier section and a ground. In an embodiment, an electrical length of the short stub is shorter than a quarter wavelength of an operation frequency of the differential amplifier circuit.