Differential Amplifier Circuitry With Auxiliary Cross-Coupling

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Solution Overview

Problem

Differential source follower circuitry suffers from gain loss and linearity degradation due to channel length modulation (CLM) effects and limited output impedance, leading to harmonic distortion in output signals.

Innovation Solution

The implementation of a differential amplifier circuitry with cross-coupled auxiliary transistors of opposite conductivity type, which increases gain and improves linearity without additional power consumption, by controlling the gate terminals of main and auxiliary transistors with component input signals and regulating currents through current sources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If cross-coupled auxiliary transistors are added to increase gain and improve linearity, then signal quality improves, but device complexity increases

Engineering Contradiction:
Improvesignal qualityVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces auxiliary transistors with opposite conductivity type (PMOS for NMOS main transistors or vice versa) to create an asymmetric structure that compensates for channel length modulation effects. This asymmetric configuration enables gain boosting and linearity improvement without requiring symmetric duplication of the entire circuit, thereby managing complexity while achieving performance enhancement.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The cross-coupled auxiliary transistors are connected in a feedback configuration where their gate terminals are connected to the drain terminals of the main transistors. This feedback mechanism automatically adjusts the auxiliary transistor currents to compensate for output impedance variations and gain loss, improving signal quality without requiring external control circuits.

Inventive Principle:
Principle #23Feedback

2Stability of the object's composition

If channel length modulation effects are compensated to improve linearity, then distortion reduces, but device complexity increases

Engineering Contradiction:
ImprovelinearityVSAvoidcircuit complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The auxiliary transistors act as intermediary elements that mediate the channel length modulation effects. By introducing these intermediate devices with opposite conductivity type, the patent creates a compensation mechanism that reduces harmonic distortion and improves linearity without requiring fundamental changes to the main transistor structure or operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Power

If output impedance is increased to reduce gain loss, then gain improves, but device complexity increases

Engineering Contradiction:
ImprovegainVSAvoidcircuit complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent merges the main transistors and auxiliary transistors into a unified differential amplifier structure where the auxiliary devices are integrated alongside the main transistors. This combined configuration allows the auxiliary transistors to contribute to gain enhancement through their cross-coupled connection, achieving higher output impedance and reduced gain loss without requiring separate gain staging circuits.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11626846B2Differential amplifier circuitry
Publication Date: 2023.04.11 SOCIONEXT INC
  • US11626846B2 patent drawing
  • US11626846B2 patent drawing
  • US11626846B2 patent drawing

AI summary

Differential amplifier circuitry including: first and second main transistors of a given conductivity type; and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.