Differential Output Buffer Biasing for High-Voltage NMOS Reliability
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Solution Overview
Problem
Conventional output buffer circuits face challenges in achieving high operational speed and reliability simultaneously, especially when operating at high power supply voltages, as they either deteriorate due to low-voltage gate oxide transistors or lack speed with high-voltage gate oxide transistors.
Innovation Solution
A differential circuit design that incorporates low-voltage gate oxide NMOS transistors with a common body node and bias voltage configuration, allowing the transistors to operate within safe voltage limits, thereby maintaining high operational speed and reliability even at high power supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If low-voltage gate oxide transistors are used to achieve high operational speed, then speed is improved, but reliability deteriorates due to gate-body voltage exceeding maximum allowable voltage
Solution Approach 1:
The patent segments the voltage handling function by separating the gate oxide thickness from the power supply voltage level. Low-voltage gate oxide transistors are used for high-speed operation while the overall circuit operates at high voltage through proper biasing and body connection techniques, dividing the voltage stress from the switching function.
Solution Approach 2:
The patent changes the body voltage parameter dynamically by coupling body electrodes to a bias voltage that tracks the source voltage. This parameter change ensures the gate-body voltage difference remains within safe limits while allowing the transistor to operate at high supply voltages for high-speed performance.
2Reliability
If high-voltage gate oxide transistors are used to operate at high power supply voltage, then reliability is improved, but operational speed decreases
Solution Approach 1:
The patent changes the effective gate oxide thickness parameter by using thin-gate-oxide transistors with proper body biasing. This allows the transistor to maintain high-speed characteristics of thin oxide devices while operating reliably at high supply voltages through controlled gate-body voltage differential.
3Strength
If power supply voltage is increased to provide high-voltage output signal, then output voltage level is improved, but transistor reliability deteriorates due to excessive gate-body voltage
Solution Approach 1:
The patent changes the body voltage parameter to track with the source voltage, maintaining a constant safe gate-body voltage differential even as the power supply voltage increases. This allows high-voltage output signals while protecting the thin gate oxide from excessive stress.
Solution Approach 2:
The body electrode acts as an intermediary that mediates between the high power supply voltage and the sensitive gate oxide. By coupling the body to a bias voltage that follows the source voltage, it shields the gate oxide from excessive voltage stress while allowing high-voltage operation.
Data Source
AI summary
An output buffer circuit includes: a differential circuit; and first and second load circuits coupled between the differential circuit and a high power supply voltage VDDH. Such a differential circuit includes first and second NMOS transistors having low-voltage gate dielectric layers susceptible to deterioration at operation above a maximum gate-body voltage VgbMAX (where VDDH>VgbMAX), respectively. Body electrodes & source electrodes are coupled to a common node. Gate electrodes are coupled to first and second differential input signals, respectively, such that voltages on drains of the first and second NMOS transistors represent results of a differential switching operation, respectively. More particularly, the drains of the first and second NMOS transistors are coupled to the first and second loads. The common node is coupled to a bias voltage such that Vgb of the first & second NMOS transistors is VgbMAX≧Vgb.