Differential Source Follower Buffer With Current Steering for PSRR
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Solution Overview
Problem
Existing buffers face challenges in maximizing performance parameters such as noise rejection, bandwidth, and power consumption, particularly in high-speed time-interleaved analog-to-digital converters, where they suffer from low power supply rejection ratio (PSRR) and feedback-induced memory effects (FME), leading to inter-symbol interference (ISI).
Innovation Solution
A differential source follower-based buffer architecture is introduced, featuring a differential source follower coupled with current steering devices and capacitors, along with a bias generator, which improves PSRR and reduces FME by using input-to-inverted-output capacitors and a DC loop for high impedance node operation, resulting in higher bandwidth and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional buffer architectures are used, then device complexity is reduced, but power supply rejection ratio (PSRR) deteriorates and bandwidth is limited
Solution Approach 1:
The buffer is divided into multiple independent source follower stages, each handling specific signal components. The first source follower processes the dominant pole frequency range while the second source follower handles higher frequency ranges, allowing each stage to be optimized for its specific function and improving overall PSRR without excessive complexity
Solution Approach 2:
A compensation capacitor is introduced as an intermediary element between the two source follower stages. This capacitor mediates the interaction between stages, providing pole-zero cancellation that improves PSRR at critical frequency ranges while maintaining stability and controlling the overall complexity of the buffer architecture
2Speed
If buffer bandwidth is increased, then signal propagation speed improves, but noise rejection capability deteriorates
Solution Approach 1:
The buffer employs dynamic compensation where the compensation capacitor's effect varies with frequency. At low frequencies, the capacitor provides strong PSRR improvement through pole-zero cancellation, while at high frequencies the inherent bandwidth of the source follower stages maintains signal propagation speed. This dynamic behavior resolves the contradiction between bandwidth and noise rejection across different frequency ranges
Solution Approach 2:
The compensation capacitor value is specifically chosen to create a zero that cancels the dominant pole of the buffer stage. By changing the effective impedance parameters at different frequencies through this capacitor, the buffer achieves high PSRR at critical frequencies while maintaining wide bandwidth for signal propagation, thus resolving the contradiction between speed and noise rejection
3Use of energy by moving object
If power consumption is reduced, then energy efficiency improves, but bandwidth and performance deteriorate
Solution Approach 1:
Instead of uniformly increasing current across the entire buffer to improve bandwidth, the invention applies partial action by using two source follower stages with different current levels. The first stage operates at lower current for DC and low-frequency signals, while the second stage provides additional bandwidth at higher frequencies. This partial application of excessive current where needed maintains bandwidth performance while minimizing overall power consumption
Data Source
AI summary
Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.