Differential Input Buffer Offset Calibration for Small-Amplitude Signals
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Solution Overview
Problem
Semiconductor devices face challenges in accurately determining logic levels of input signals with small amplitudes due to input offset in differential amplifiers caused by random variations in transistor thresholds, which existing adjustment methods fail to fully address.
Innovation Solution
Incorporating a calibration control circuit that supplies calibration signals to adjust the input offsets of differential amplifiers within the input buffer circuit, using code signals stored in a nonvolatile fuse circuit to fine-tune the amplifiers and ensure accurate signal amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-sensitivity differential amplifier is used to determine logic levels of small amplitude signals, then signal detection capability is improved, but input offset due to transistor threshold variations deteriorates measurement precision
Solution Approach 1:
The patent applies preliminary action by performing offset calibration before normal signal amplification. The calibration control circuit pre-adjusts the differential amplifier's offset using stored calibration codes, ensuring the amplifier is properly calibrated before processing actual input signals. This preliminary calibration action eliminates offset errors that would otherwise degrade measurement precision.
Solution Approach 2:
The patent changes the operating parameters of the differential amplifier by applying calibration voltages to adjust the gate-source voltages of transistors. The calibration control circuit varies these parameters to compensate for threshold variations, thereby maintaining reliable operation despite manufacturing tolerances. This parameter adjustment directly addresses the input offset stability issue.
2Measurement precision
If adjustment codes are used to fine-tune differential amplifier offset during manufacturing, then input offset is reduced, but device complexity and calibration process time increase
Solution Approach 1:
The patent uses copying by storing calibration codes in a nonvolatile memory device that replicates the necessary adjustment information. Instead of complex real-time adjustment mechanisms, the system copies pre-determined calibration data into the memory, which then supplies these codes to the calibration control circuit. This simplifies the overall device complexity while maintaining adjustment accuracy.
Solution Approach 2:
The calibration system implements self-service by automatically applying calibration codes without requiring external manual intervention. The calibration control circuit autonomously retrieves codes from memory and applies them to adjust the differential amplifier offset, eliminating the need for complex external calibration equipment or manual adjustment procedures.
3Measurement precision
If calibration signals are supplied to adjust differential amplifier offsets, then signal amplification accuracy is improved, but additional circuit components and power consumption increase
Solution Approach 1:
The patent applies periodic action by performing calibration only when necessary (e.g., during initialization or when offset drift is detected) rather than continuously. The calibration control circuit activates calibration signals periodically or event-driven, allowing the differential amplifier to operate in normal amplification mode during intervals between calibration events. This reduces overall power consumption while maintaining signal amplification accuracy.
Solution Approach 2:
The patent extracts the calibration function into a separate, dedicated calibration control circuit that operates independently from the main signal amplification path. This extraction allows the calibration subsystem to be optimized for low-power operation, using minimal power for brief calibration bursts while the main amplifier continues normal operation without continuous calibration overhead.
Data Source
AI summary
Disclosed herein is an apparatus that includes first and second signal lines; a first differential amplifier having an inverting input node receiving an input signal, a non-inverting input node receiving a reference potential, and an output node connected to the first signal line; a second differential amplifier having an inverting input node receiving the reference potential, a non-inverting input node receiving the input signal, and an output node connected to the second signal line; a level shift circuit cross-coupled to the first and second signal lines; a first replica circuit connected to the first signal line; a second replica circuit connected to the second signal line; and a first switch circuit configured to activate one of the level shift circuit, the first replica circuit, and the second replica circuit.