Differential Analog Input Buffer With Power Noise Rejection
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Solution Overview
Problem
Existing analog input buffers face performance degradation due to power supply noise, which affects the output signal and is not effectively addressed by current technologies.
Innovation Solution
The implementation of a differential signal buffer using power regulators in conjunction with analog buffer circuits to enhance power supply noise rejection, including the use of NMOS and PMOS transistors and level shifters to adjust voltage and current based on differential signals, thereby improving common-mode signal rejection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a conventional analog input buffer is used, then the buffer provides basic signal isolation and gain, but power supply noise directly affects the output signal quality
Solution Approach 1:
The patent introduces power regulator circuits as intermediary components between the power supply and the buffer circuits. These regulators act as mediators that filter and condition the power supply voltage before it reaches the buffer, thereby reducing power supply noise without fundamentally changing the buffer's core functionality. This resolves the contradiction by adding noise rejection capability while maintaining relatively simple buffer circuitry.
Solution Approach 2:
The patent divides the buffer system into separate functional modules: buffer circuits for signal processing and power regulator circuits for noise filtering. This segmentation allows each component to be optimized independently - the buffer for gain and isolation, and the regulators for noise rejection - thereby achieving high noise immunity without excessive overall complexity.
2Object-affected harmful factors
If power regulators are added to reduce power supply noise, then noise rejection improves, but device complexity increases
Solution Approach 1:
Power regulator circuits are introduced as intermediary components between the power supply and the buffer circuits. These regulators condition the power supply voltage to reduce noise before it reaches the buffer, resolving the contradiction by adding noise rejection capability while maintaining relatively simple buffer circuitry.
Solution Approach 2:
The buffer system is divided into separate functional modules: buffer circuits for signal processing and power regulator circuits for noise filtering. This segmentation allows each component to be optimized independently, achieving high noise immunity without excessive overall complexity.
3Object-affected harmful factors
If differential buffering is implemented, then common-mode signal rejection improves, but device complexity increases
Solution Approach 1:
The patent employs differential buffer circuits with asymmetric transistor configurations (NMOS and PMOS devices) that are optimized for rejecting common-mode signals. By using complementary transistor pairs with different characteristics, the circuit achieves superior common-mode rejection while maintaining a relatively compact structure that doesn't excessively increase complexity.
Data Source
AI summary
A differential signal input buffer is disclosed. The differential signal input buffer may receive a differential signal that includes a first signal and a second signal and may be divided into a first section and a second section and. The first section may buffer and/or amplify the first signal based on a first level-shifted second signal. The second section may buffer and/or amplify the second signal based on a first level-shifted first signal. In some implementations, the first section may buffer and/or amplify the first signal based on a second level-shifted second signal. Further, in some implementations, the second section may buffer and/or amplify the second signal based on a second level-shifted first signal.